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[fpgaboy.git] / Sound1.v
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1`define ADDR_NR10 16'hFF10
2`define ADDR_NR11 16'hFF11
3`define ADDR_NR12 16'hFF12
4`define ADDR_NR13 16'hFF13
5`define ADDR_NR14 16'hFF14
6
7module Sound1(
8 input core_clk,
9 input wr,
10 input rd,
11 input [15:0] addr,
12 inout [7:0] data,
13 input cntclk,
14 input lenclk,
15 input en,
16 output [3:0] snd_data
17 );
18
19 /* can be optimized as register file */
20 reg [7:0] nr10, nr11, nr12, nr13, nr14;
21 reg [10:0] counter = 0;
22 reg [4:0] lencnt = 0;
23 reg [3:0] delta = 4'b1111;
24 reg [2:0] dutycnt;
25 reg [3:0] snd_out = 0;
26
27 assign snd_data = en ? snd_out : 0;
28
29 assign data = rd ?
30 addr == `ADDR_NR10 ? nr10 :
31 addr == `ADDR_NR11 ? nr11 :
32 addr == `ADDR_NR12 ? nr12 :
33 addr == `ADDR_NR13 ? nr13 :
34 addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
35 : 8'bzzzzzzzz;
36
37 always @ (negedge core_clk) begin
38 if(en && wr) begin
39 case(addr)
40 `ADDR_NR10: nr10 <= data;
41 `ADDR_NR11: nr11 <= data;
42 `ADDR_NR12: nr12 <= data;
43 `ADDR_NR13: nr13 <= data;
44 `ADDR_NR14: nr14 <= data;
45 endcase
46 end
47 else if(!en) begin
48 nr10 <= 8'h80;
49 nr11 <= 8'h3F;
50 nr12 <= 8'h00;
51 nr13 <= 8'hFF;
52 nr14 <= 8'hBF;
53 end
54 end
55
56 always @ (posedge cntclk) begin
57 if(counter)
58 counter <= counter - 1;
59 else begin
60 counter <= ~{nr14[2:0],nr13} + 1; /* possible A */
61 dutycnt <= dutycnt + 1;
62 end
63
64 case (nr11[7:6])
65 2'b00: snd_out <= dutycnt ? 0 : delta; /* probable A */
66 2'b01: snd_out <= (dutycnt[2:1] == 2'b0) ? delta : 0;
67 2'b10: snd_out <= dutycnt[2] ? delta : 0;
68 2'b11: snd_out <= (dutycnt[2:1] == 2'b0) ? 0 : delta;
69 endcase
70 end
71
72 always @ (posedge lenclk) begin
73 if(lencnt)
74 lencnt <= lencnt - 1; /* possible A */
75 else
76 lencnt <= ~nr11[4:0] + 1;
77 end
78
79endmodule
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