git.joshuawise.com / fpgaboy.git / blame
| Commit | Line | Data |
|---|---|---|
| 81358c71 JW |
1 | //////////////////////////////////////////////////////////////////////////////// |
| 2 | // Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. | |
| 3 | //////////////////////////////////////////////////////////////////////////////// | |
| 4 | // ____ ____ | |
| 5 | // / /\/ / | |
| 6 | // /___/ \ / Vendor: Xilinx | |
| 7 | // \ \ \/ Version : 10.1 | |
| 8 | // \ \ Application : xaw2verilog | |
| 9 | // / / Filename : CPUDCM.v | |
| 10 | // /___/ /\ Timestamp : 03/31/2008 23:51:44 | |
| 11 | // \ \ / \ | |
| 12 | // \___\/\___\ | |
| 13 | // | |
| 14 | //Command: xaw2verilog -intstyle /home/joshua/projects/fpga/FPGABoy/CPUDCM.xaw -st CPUDCM.v | |
| 15 | //Design Name: CPUDCM | |
| 16 | //Device: xc3s500e-5fg320 | |
| 17 | // | |
| 18 | // Module CPUDCM | |
| 19 | // Generated by Xilinx Architecture Wizard | |
| 20 | // Written for synthesis tool: XST | |
| 21 | // Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI | |
| 22 | // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 4.90 ns | |
| 23 | `timescale 1ns / 1ps | |
| 24 | ||
| 25 | module CPUDCM(CLKIN_IN, | |
| 26 | CLKFX_OUT, | |
| 27 | CLKIN_IBUFG_OUT, | |
| 28 | LOCKED_OUT); | |
| 29 | ||
| 30 | input CLKIN_IN; | |
| 31 | output CLKFX_OUT; | |
| 32 | output CLKIN_IBUFG_OUT; | |
| 33 | output LOCKED_OUT; | |
| 34 | ||
| 35 | wire CLKFX_BUF; | |
| 36 | wire CLKIN_IBUFG; | |
| 37 | wire GND_BIT; | |
| 38 | ||
| 39 | assign GND_BIT = 0; | |
| 40 | assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; | |
| 41 | BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), | |
| 42 | .O(CLKFX_OUT)); | |
| 43 | IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), | |
| 44 | .O(CLKIN_IBUFG)); | |
| 45 | DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), | |
| 46 | .CLKIN(CLKIN_IBUFG), | |
| 47 | .DSSEN(GND_BIT), | |
| 48 | .PSCLK(GND_BIT), | |
| 49 | .PSEN(GND_BIT), | |
| 50 | .PSINCDEC(GND_BIT), | |
| 51 | .RST(GND_BIT), | |
| 52 | .CLKDV(), | |
| 53 | .CLKFX(CLKFX_BUF), | |
| 54 | .CLKFX180(), | |
| 55 | .CLK0(), | |
| 56 | .CLK2X(), | |
| 57 | .CLK2X180(), | |
| 58 | .CLK90(), | |
| 59 | .CLK180(), | |
| 60 | .CLK270(), | |
| 61 | .LOCKED(LOCKED_OUT), | |
| 62 | .PSDONE(), | |
| 63 | .STATUS()); | |
| 64 | defparam DCM_SP_INST.CLK_FEEDBACK = "NONE"; | |
| 65 | defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; | |
| 66 | defparam DCM_SP_INST.CLKFX_DIVIDE = 25; | |
| 67 | defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; | |
| 68 | defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; | |
| 69 | defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; | |
| 70 | defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; | |
| 71 | defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; | |
| 72 | defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; | |
| 73 | defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; | |
| 74 | defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; | |
| 75 | defparam DCM_SP_INST.FACTORY_JF = 16'hC080; | |
| 76 | defparam DCM_SP_INST.PHASE_SHIFT = 0; | |
| 77 | defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; | |
| 78 | endmodule |