Joshua Wise's Git repositories - firearm.git/search

]> Joshua Wise's Git repositories - firearm.git/search

2010-03-11	Joshua Wise	Memory: Input renaming pass.	commit \| commitdiff \| tree
2010-03-11	Joshua Wise	Execute: Pass 1 repiping finished.	commit \| commitdiff \| tree
2010-03-11	Joshua Wise	tests/Makefile: Build without THUMB support. This...	commit \| commitdiff \| tree
2010-03-10	Joshua Wise	Global: More re-piping, and a bugfix for a bug recently...	commit \| commitdiff \| tree
2010-03-10	Joshua Wise	tests/Makefile: Build the testbench by default with...	commit \| commitdiff \| tree
2010-03-09	Joshua Wise	Issue: AUTORESET.	commit \| commitdiff \| tree
2010-03-09	Joshua Wise	Issue: Fix pipe names.	commit \| commitdiff \| tree
2010-02-27	Joshua Wise	Regfile: Rename signals for correct pipe stages.	commit \| commitdiff \| tree
2010-02-22	Joshua Wise	ICache: Change cache_data to block RAM (yay!).	commit \| commitdiff \| tree
2010-02-22	Joshua Wise	ICache, Fetch: Re-pipe things such that the icache...	commit \| commitdiff \| tree
2010-02-22	Joshua Wise	xst/Console: Change divisors.	commit \| commitdiff \| tree
2010-02-22	Joshua Wise	Fetch, ICache: Autoize ICache/Fetch interface, and...	commit \| commitdiff \| tree
2010-02-22	Joshua Wise	Makefile: Add 'auto' target to verilog-modeify.	commit \| commitdiff \| tree
2010-02-21	Joshua Wise	build system: Produce a top level makefile that invokes...	commit \| commitdiff \| tree
2010-02-21	Joshua Wise	Testbench: use 'urxvt', not 'rxvt'.	commit \| commitdiff \| tree

FireARM pipelined ARM-like CPU implementation in Verilog

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