From 6d18bf2758e61202ba514a431bbcfca827dd7d1e Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:39:59 -0500
Subject: [PATCH 01/16] Memory: Add STRB support, en manera de A.

---
 Memory.v | 61 +++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/Memory.v b/Memory.v
index 7ca786e..eccddb2 100644
--- a/Memory.v
+++ b/Memory.v
@@ -65,7 +65,7 @@ module Memory(
 	reg [3:0] next_write_num;
 	reg [31:0] next_write_data;
 
-	reg [2:0] lsr_state = 3'b001, next_lsr_state;
+	reg [3:0] lsr_state = 4'b0001, next_lsr_state;
 	reg [31:0] align_s1, align_s2, align_rddata;
 
 	reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
@@ -79,6 +79,9 @@ module Memory(
 
 	reg [31:0] swp_oldval, next_swp_oldval;
 	reg [1:0] swp_state = 2'b01, next_swp_state;
+	
+	reg do_rd_data_latch;
+	reg [31:0] rd_data_latch = 32'hxxxxxxxx;
 
 	always @(posedge clk)
 	begin
@@ -100,6 +103,8 @@ module Memory(
 		lsm_state <= next_lsm_state;
 		lsr_state <= next_lsr_state;
 		lsrh_state <= next_lsrh_state;
+		if (do_rd_data_latch)
+			rd_data_latch <= rd_data;
 		prevaddr <= addr;
 	end
 	
@@ -120,6 +125,7 @@ module Memory(
 		busaddr = 32'hxxxxxxxx;
 		data_size = 3'bxxx;
 		outstall = 1'b0;
+		do_rd_data_latch = 0;
 		next_write_reg = write_reg;
 		next_write_num = write_num;
 		next_write_data = write_data;
@@ -248,42 +254,69 @@ module Memory(
 			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 			/* select byte or word */
 			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-			wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+			wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
 			data_size = insn[22] ? 3'b001 : 3'b100;
 			case(lsr_state)
-			3'b001: begin
-				rd_req = insn[20] /* L */;
-				wr_req = ~insn[20] /* L */;
+			4'b0001: begin
+				rd_req = insn[20] /* L */ || insn[22] /* B */;
+				wr_req = !insn[20] /* L */ && !insn[22]/* B */;
 				next_write_reg = insn[20] /* L */;
 				next_write_num = insn[15:12];
 				if(insn[20] /* L */) begin
-					next_write_data = align_rddata;
+					next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
 				end
-				if(insn[21] /* W */ | !insn[24] /* P */) begin
+				if (insn[22] /* B */ && !insn[20] /* L */) begin
+					do_rd_data_latch = 1;
+					outstall = 1'b1;
+					if (!rw_wait)
+						next_lsr_state = 4'b0010;	/* XXX: One-hot, my ass. */
+				end else if(insn[21] /* W */ | !insn[24] /* P */) begin
 					outstall = 1'b1;
 					if(!rw_wait)
-						next_lsr_state = 3'b010;
+						next_lsr_state = 4'b0100;
 				end
 				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
 			end
-			3'b010: begin
+			4'b0010: begin
+				$display("LDRSTR: Handling STRB");
 				outstall = 1;
+				rd_req = 0;
+				wr_req = 1;
+				next_write_reg = 0;
+				case (busaddr[1:0])
+				2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+				2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+				2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+				2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+				endcase
+				if(insn[21] /* W */ | !insn[24] /* P */) begin
+					if(!rw_wait)
+						next_lsr_state = 4'b0100;
+				end else if (!rw_wait)
+					next_lsr_state = 4'b1000;
+			end
+			4'b0100: begin
+				outstall = 1;
+				rd_req = 0;
+				wr_req= 0;
 				next_outbubble = 0;
 				next_write_reg = 1'b1;
 				next_write_num = insn[19:16];
 				next_write_data = addr;
-				next_lsr_state = 3'b100;
+				next_lsr_state = 4'b1000;
 			end
-			3'b100: begin
+			4'b1000: begin
+				rd_req = 0;
+				wr_req= 0;
 				outstall = 0;
-				next_lsr_state = 3'b001;
+				next_lsr_state = 4'b0001;
 			end
 			default: begin end
 			endcase
 			
-			if ((lsr_state == 3'b001) && flush) begin	/* Reject it. */
+			if ((lsr_state == 4'b0001) && flush) begin	/* Reject it. */
 				outstall = 1'b0;
-				next_lsr_state = 3'b001;
+				next_lsr_state = 4'b0001;
 			end
 		end
 		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
-- 
2.39.2


From 7282e8f84e4f5aecab6e57c2086785bbd6d48748 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:40:32 -0500
Subject: [PATCH 02/16] Terminal: Add support for reading characters.

---
 Terminal.v    | 11 +++++++++++
 testbench.cpp | 47 ++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/Terminal.v b/Terminal.v
index 89b19d5..dd041d0 100644
--- a/Terminal.v
+++ b/Terminal.v
@@ -12,6 +12,8 @@ module Terminal(
 	/* Terminal pretends to be cp5. */
 	reg towrite = 0;
 	reg [7:0] data = 0;
+	reg [8:0] indata = 0;	/* High bit is if data is present. */
+	reg didread = 0;
 	
 	always @(*)
 	begin
@@ -19,16 +21,25 @@ module Terminal(
 		data = 8'hxx;
 		cp_ack = 0;
 		cp_busy = 0;
+		cp_read = 0;
+		didread = 0;
 		if (cp_req && (cp_rnw == 0) && (cp_insn[27:24] == 4'b1110) && (cp_insn[19:16] == 4'b0000) && (cp_insn[11:8] == 4'h5))
 		begin
 			towrite = 1;
 			data = cp_write[7:0];
 			cp_ack = 1;
+		end else if (cp_req && (cp_rnw == 1) && (cp_insn[27:24] == 4'b1110) && (cp_insn[19:16] == 4'b0001) && (cp_insn[11:8] == 4'h5))
+		begin
+			cp_read = {23'h0, indata[8:0]};
+			cp_ack = 1;
+			didread = cp_insn[7:5] == 1;
 		end
 	end
 `ifdef verilator	
 	always @(posedge clk)
 		if (towrite)
 			$c("{extern void term_output(unsigned char d); term_output(",data,");}");
+		else if (didread || !indata[8])
+			indata = $c("({extern unsigned int term_input(); term_input();})");
 `endif
 endmodule
diff --git a/testbench.cpp b/testbench.cpp
index 53be841..e89de38 100644
--- a/testbench.cpp
+++ b/testbench.cpp
@@ -3,26 +3,51 @@
 #define _XOPEN_SOURCE
 #include <stdlib.h>
 #include <fcntl.h>
+#include <termios.h>
 
 Vsystem *top;
 
+int ptyfd = -1;
+
+void openpty()
+{
+	int fd = posix_openpt(O_RDWR);
+	char b[128];
+	struct termios kbdios;
+	
+	grantpt(fd);  
+	fcntl(fd, F_SETFD, 0);	/* clear close-on-exec */
+	tcgetattr(fd, &kbdios);
+	kbdios.c_lflag &= ~(ECHO|ECHONL|ICANON|ISIG|IEXTEN);
+	tcsetattr(fd, TCSANOW, &kbdios);
+	sprintf(b, "rxvt -pty-fd %d -bg black -fg white -title \"Output terminal\" &", fd);
+	system(b);
+	unlockpt(fd);
+	ptyfd = open(ptsname(fd), O_RDWR | O_NONBLOCK);
+	close(fd);
+}
+
+unsigned int term_input()
+{
+	int rv;
+	unsigned char c;
+	if (ptyfd == -1)
+		openpty();
+	rv = read(ptyfd, &c, 1);
+	if (rv < 0)
+		return 0;
+	return 0x100 | c;
+}
+
 void term_output(unsigned char d)
 {
 	int fd = posix_openpt(O_RDWR);
 	static int fd2 = -1;
 	char b[128];
 
-	if (fd2 == -1)
-	{
-		grantpt(fd);  
-		fcntl(fd, F_SETFD, 0);	/* clear close-on-exec */
-		sprintf(b, "rxvt -pty-fd %d -bg black -fg white -title \"Output terminal\" &", fd);
-		system(b);
-		unlockpt(fd);
-		fd2 = open(ptsname(fd), O_RDWR);
-		close(fd);
-	}
-	write(fd2, &d, 1);
+	if (ptyfd == -1)
+		openpty();
+	write(ptyfd, &d, 1);
 }
 
 unsigned int main_time = 0;
-- 
2.39.2


From fa1c06764950e6c965ed8ce1dcf180ae1ba2df1a Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:45:12 -0500
Subject: [PATCH 03/16] tests/miniblarg: Make the ROM easier to read.

---
 tests/miniblarg.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/tests/miniblarg.c b/tests/miniblarg.c
index 8fdff0f..e32989c 100644
--- a/tests/miniblarg.c
+++ b/tests/miniblarg.c
@@ -13,7 +13,24 @@ int abort()
 int *ROM()
 {
 	static int a[] = {
-		3632, 9, 3584, 57, 3600, 16384, 3616, 65535, 11792, 20018, 19970, 24114, 592, 8, 3584, 10, 11792, 65535};
+		0x0E30,	/* 0 */
+		0x0009,	/* 1 */
+		0x0E00,	/* 2 */
+		0x0039,	/* 3 */
+		0x0E10,	/* 4 */
+		0x4000,	/* 5 */
+		0x0E20,	/* 6 */
+		0xFFFF,	/* 7 */
+		0x2E10,	/* 8 */
+		0x4E32,	/* 9 */
+		0x4E02,	/* A */
+		0x5E32,	/* B */
+		0x0250,	/* C */
+		0x0008,	/* D */
+		0x0E00,	/* E */
+		0x000A,	/* F */
+		0x2E10,	/* 10 */
+		0xFFFF};	/* 11 */
 	return a;
 }
 
-- 
2.39.2


From 1783621cc5b0d6411aa33cf9961b29f8e440e605 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:53:37 -0500
Subject: [PATCH 04/16] Add a .gitattributes file to force hex files to be
 binary-like.

---
 .gitattributes | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 .gitattributes

diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..c8120ab
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.hex -crlf -diff -merge
\ No newline at end of file
-- 
2.39.2


From 85de10c4daf4c84d590f8c649f746ef5625965f6 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:54:01 -0500
Subject: [PATCH 05/16] tests/*.hex: Update hex files.

---
 ram.hex          |    2 +-
 tests/u-boot.hex | 1478 +++++++++++++++++++++++-----------------------
 2 files changed, 744 insertions(+), 736 deletions(-)

diff --git a/ram.hex b/ram.hex
index 5d115b1..96b3cdf 120000
--- a/ram.hex
+++ b/ram.hex
@@ -1 +1 @@
-tests/ram.hex
\ No newline at end of file
+tests/u-boot.hex
\ No newline at end of file
diff --git a/tests/u-boot.hex b/tests/u-boot.hex
index 17c2466..7003855 100644
--- a/tests/u-boot.hex
+++ b/tests/u-boot.hex
@@ -16,8 +16,8 @@ e59ff014
 deadbeef
 00100000
 00100000
-001107e4
-00112114
+00110804
+00112134
 e3a00052
 ee000510
 e3a00053
@@ -278,9 +278,9 @@ e1500003
 e3a03000
 e1a00003
 e1a0f00e
-001107f0
-001107e8
-001107ec
+00110810
+00110808
+0011080c
 e1a0f00e
 e1a0f00e
 e1a0f00e
@@ -291,7 +291,7 @@ e1a0f00e
 e59f0004
 eb00103c
 eafffffe
-0010cd90
+0010cdb0
 e92d4010
 e5983000
 e5934020
@@ -302,16 +302,16 @@ e59f100c
 eb001d82
 e3a00000
 e8bd8010
-0010cdbc
-0010eff4
+0010cddc
+0010f014
 e52de004
 e59f000c
 e59f100c
 eb00103d
 e3a00000
 e49df004
-0010cdc4
-0010c628
+0010cde4
+0010c648
 e92d4070
 e24dd040
 e59f0044
@@ -333,7 +333,7 @@ e3a00000
 e5853000
 e28dd040
 e8bd8070
-0010cdcc
+0010cdec
 0001c200
 e92d40f0
 e59f4178
@@ -434,15 +434,15 @@ eb001948
 eafffffd
 00100044
 00100048
-0010fa48
-001107e4
-001107e8
-001107ec
-001107f0
-0010cdd8
-0010cde0
-0010cde8
-001107f4
+0010fa68
+00110804
+00110808
+0011080c
+00110810
+0010cdf8
+0010ce00
+0010ce08
+00110814
 e1a0f00e
 e3a00000
 e1a0f00e
@@ -515,23 +515,23 @@ e58dc000
 eb000f70
 e28dd088
 e8bd8030
-0010c66c
-0010cdf4
-0010ce3c
-0010ce60
-0010ce90
-0010cec0
-0010ced4
-0010ced0
-0010e334
-0010ced8
+0010c68c
+0010ce14
+0010ce5c
+0010ce80
+0010ceb0
+0010cee0
+0010cef4
+0010cef0
+0010e354
+0010cef8
 e52de004
 e59f000c
 eb002135
 e3a00000
 e49de004
 eafffeea
-0010cef8
+0010cf18
 e92d4010
 e1a04000
 e59f0010
@@ -540,7 +540,7 @@ e1a00004
 ebffffa3
 e8bd4010
 eafffff0
-0010cf0c
+0010cf2c
 e92d4010
 e1a04000
 e59f0010
@@ -549,7 +549,7 @@ e1a00004
 ebffff9a
 e8bd4010
 eaffffe7
-0010cf20
+0010cf40
 e92d4010
 e1a04000
 e59f0010
@@ -558,7 +558,7 @@ e1a00004
 ebffff91
 e8bd4010
 eaffffde
-0010cf38
+0010cf58
 e92d4010
 e1a04000
 e59f0010
@@ -567,7 +567,7 @@ e1a00004
 ebffff88
 e8bd4010
 eaffffd5
-0010cf44
+0010cf64
 e92d4010
 e1a04000
 e59f0010
@@ -576,7 +576,7 @@ e1a00004
 ebffff7f
 e8bd4010
 eaffffcc
-0010cf50
+0010cf70
 e92d4010
 e1a04000
 e59f0010
@@ -585,7 +585,7 @@ e1a00004
 ebffff76
 e8bd4010
 eaffffc3
-0010cf60
+0010cf80
 e92d4010
 e1a04000
 e59f0010
@@ -594,7 +594,7 @@ e1a00004
 ebffff6d
 e8bd4010
 eaffffba
-0010cf74
+0010cf94
 e1a03800
 e1a03823
 e20300ff
@@ -687,8 +687,8 @@ e1a02a22
 e8bd4010
 ea0021c2
 0000ffff
-0010d08c
-0010d094
+0010d0ac
+0010d0b4
 e92d4010
 e24dd008
 e1a04001
@@ -707,7 +707,7 @@ e58dc004
 eb0021af
 e28dd008
 e8bd8010
-0010d098
+0010d0b8
 e92d4010
 e24dd010
 e1a0100d
@@ -822,14 +822,14 @@ e3500000
 eafffff2
 e1a00004
 e8bd84f0
-0010d0a4
-0010d100
+0010d0c4
+0010d120
 27051956
-0010d0ac
-0010d0c0
-0010d0d0
+0010d0cc
 0010d0e0
 0010d0f0
+0010d100
+0010d110
 e3520001
 e92d4010
 d3a04000
@@ -846,7 +846,7 @@ e1a00004
 e3a01000
 e8bd4010
 eaffff86
-0010d124
+0010d144
 e1a03000
 e52de004
 e1a00001
@@ -886,10 +886,10 @@ e2534000
 eb000dfd
 e1a00004
 e8bd8070
-0010d1c0
-0010d1cc
+0010d1e0
+0010d1ec
 00100d44
-0010d1f4
+0010d214
 e1a02000
 e2003cff
 e1a00c00
@@ -917,7 +917,7 @@ e1a0e00f
 e1a0f004
 e3a00001
 e8bd8010
-0010d2d8
+0010d2f8
 001064c4
 e92d4ef0
 e3500000
@@ -998,9 +998,9 @@ e1a0f004
 e3a00001
 e28dd00c
 e8bd8ef0
-0010d314
-0010e334
-0010d320
+0010d334
+0010e354
+0010d340
 001064c4
 e590000c
 eaffff8d
@@ -1227,29 +1227,29 @@ e5825048
 e3a00000
 e28dd00c
 e8bd8ef0
-001107fc
-0010d0a4
+0011081c
+0010d0c4
 00100e14
 00100e10
-001107f4
+00110814
 001064c4
-0010d36c
+0010d38c
 27051956
-0010d3a0
-0010d3b4
-0010d3cc
-0010d3e8
-0010d3f8
-0010d3fc
-0011084c
+0010d3c0
+0010d3d4
+0010d3ec
+0010d408
+0010d418
 0010d41c
-00110800
-0010d440
-0010d464
+0011086c
+0010d43c
+00110820
+0010d460
 0010d484
-0010d4a8
-00110860
-0010d4cc
+0010d4a4
+0010d4c8
+00110880
+0010d4ec
 e24dd010
 e92d4ef0
 e24dd004
@@ -1336,13 +1336,13 @@ e28dd004
 e8bd4ef0
 e28dd010
 e1a0f00e
-0010d4f4
-0010d504
-0010d3f8
-0010d518
-0010d534
+0010d514
+0010d524
+0010d418
+0010d538
+0010d554
 001064c4
-0010d57c
+0010d59c
 e92d44f0
 e1a05000
 e24dd014
@@ -1454,14 +1454,14 @@ e3a04000
 e1a00004
 e28dd014
 e8bd84f0
-0010fabc
-001107fc
-0010d5a0
-0010d1c0
-0010fa70
-0010d5cc
-0010d5f0
+0010fadc
+0011081c
+0010d5c0
+0010d1e0
+0010fa90
+0010d5ec
 0010d610
+0010d630
 e92d4ef0
 e59fc200
 e59cc000
@@ -1552,7 +1552,7 @@ e1a0000a
 e1a01009
 e1a02006
 e1a03007
-eb002a05
+eb002a0b
 ea000009
 e3700003
 1a000007
@@ -1589,15 +1589,15 @@ e1a0000a
 e1a01009
 e1a02006
 e1a03007
-eb0029e0
+eb0029e6
 e3a00001
 e28dd018
 e8bd8ef0
-001107f8
-0010fa70
-001107fc
-0010d630
-0010d66c
+00110818
+0010fa90
+0011081c
+0010d650
+0010d68c
 001064c4
 e92d4ef0
 e24dd008
@@ -1644,11 +1644,11 @@ e1550007
 e3a00000
 e28dd008
 e8bd8ef0
-0010d91c
-001109a4
-0010fbbc
-0010d938
-0010d94c
+0010d93c
+001109c4
+0010fbdc
+0010d958
+0010d96c
 e3a00000
 e1a0f00e
 e3a00000
@@ -1675,9 +1675,9 @@ e3a00001
 e8bd8030
 e3a00000
 e8bd8030
-0010ced4
-0010ced0
-0010d1c0
+0010cef4
+0010cef0
+0010d1e0
 e5d03000
 e353002a
 11a0f00e
@@ -1821,8 +1821,8 @@ e59f000c
 eb000a56
 e3a00000
 e8bd8ef0
-0010fb4c
-0010de70
+0010fb6c
+0010de90
 e3520004
 e92d4010
 e1a01002
@@ -1863,8 +1863,8 @@ e3a00000
 e2700001
 33a00000
 e8bd8010
-0010d1c0
-0010de88
+0010d1e0
+0010dea8
 e2003060
 e3530040
 e20020ff
@@ -1894,9 +1894,9 @@ e5832000
 e59f300c
 e5831000
 e1a0f00e
-0011097c
-0011096c
-00110974
+0011099c
+0011098c
+00110994
 e59f301c
 e5933000
 e3530000
@@ -1906,8 +1906,8 @@ e20000ff
 04c30001
 05823000
 e1a0f00e
-0011096c
-00110974
+0011098c
+00110994
 e59f2018
 e3a03000
 e52de004
@@ -1916,8 +1916,8 @@ e59f300c
 e1a0e00f
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@@ -1931,12 +1931,12 @@ e5831000
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@@ -1950,12 +1950,12 @@ e5831000
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@@ -1979,9 +1979,9 @@ e59f300c
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@@ -1993,8 +1993,8 @@ e3540000
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@@ -2123,15 +2123,15 @@ e5c26001
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@@ -2155,8 +2155,8 @@ e5c42005
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@@ -2180,8 +2180,8 @@ e5c42005
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@@ -2229,11 +2229,11 @@ e1a0100b
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@@ -2292,7 +2292,7 @@ eb001386
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@@ -2507,13 +2507,13 @@ e3500000
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@@ -2549,12 +2549,12 @@ e1a01002
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@@ -2566,39 +2566,39 @@ e1a00004
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@@ -2673,7 +2673,7 @@ ea000016
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@@ -2683,7 +2683,7 @@ e28d5fc5
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@@ -2700,7 +2700,7 @@ e3530000
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@@ -2752,7 +2752,7 @@ e3500000
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@@ -2769,17 +2769,17 @@ e5834000
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@@ -2795,8 +2795,8 @@ e5931000
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@@ -2840,9 +2840,9 @@ eb001730
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@@ -2912,10 +2912,10 @@ e3a0000a
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@@ -2977,7 +2977,7 @@ e2522001
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@@ -3031,9 +3031,9 @@ e2522001
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@@ -3130,17 +3130,17 @@ eb00053a
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@@ -3191,8 +3191,8 @@ e2533001
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@@ -3279,16 +3279,16 @@ e5835000
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@@ -3352,7 +3352,7 @@ eb001530
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@@ -3369,17 +3369,17 @@ e5836000
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@@ -3401,14 +3401,14 @@ e3a00064
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@@ -3599,11 +3599,11 @@ e1a01004
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@@ -3787,21 +3787,21 @@ e3a01000
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@@ -3817,7 +3817,7 @@ e59f0008
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@@ -3835,7 +3835,7 @@ e58dc00c
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@@ -3927,10 +3927,10 @@ baffffd2
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@@ -4059,22 +4059,22 @@ e1a0a006
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@@ -4149,8 +4149,8 @@ e0613003
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@@ -4285,19 +4285,19 @@ baffffe4
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@@ -4337,7 +4337,7 @@ e59f300c
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@@ -4348,7 +4348,7 @@ e7933100
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@@ -4358,7 +4358,7 @@ e7933100
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@@ -4369,7 +4369,7 @@ e1a00001
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@@ -4379,22 +4379,22 @@ e1a00001
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@@ -4453,7 +4453,7 @@ e1a01000
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@@ -4570,15 +4570,15 @@ e354000c
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@@ -4591,7 +4591,7 @@ e59d1128
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@@ -4615,7 +4615,7 @@ e3130002
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@@ -4637,11 +4637,11 @@ e5832000
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@@ -4677,7 +4677,7 @@ e5801000
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@@ -4732,7 +4732,7 @@ e1a01006
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@@ -4745,8 +4745,8 @@ e2811004
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@@ -4789,10 +4789,10 @@ e5831000
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@@ -4843,9 +4843,9 @@ e5823000
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@@ -4989,11 +4989,11 @@ e5840008
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@@ -5386,14 +5386,14 @@ ea000000
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@@ -5415,7 +5415,7 @@ ebfffe5f
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@@ -5526,7 +5526,7 @@ e3a01000
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@@ -5810,7 +5810,7 @@ e5823004
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@@ -5818,7 +5818,7 @@ e3530000
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@@ -5836,7 +5836,7 @@ e59f200c
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@@ -5873,8 +5873,8 @@ e5933000
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@@ -5894,7 +5894,7 @@ e49df004
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@@ -5904,7 +5904,7 @@ e3a00000
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@@ -5957,9 +5957,9 @@ e8bd8010
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@@ -5993,26 +5993,26 @@ e20020ff
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@@ -6039,26 +6039,26 @@ e1a02000
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@@ -6125,7 +6125,7 @@ ea000a5b
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@@ -6138,7 +6138,7 @@ ea000a4e
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@@ -6244,16 +6244,16 @@ e1a0200a
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@@ -6436,17 +6436,17 @@ e3500000
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 e1a0f00e
 e92d4010
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@@ -6482,7 +6482,7 @@ e3a01010
 ebfff821
 e1a00004
 e8bd8010
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 e1a05000
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@@ -6692,9 +6692,9 @@ e3e09000
 e1a00009
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 e3520001
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@@ -6725,8 +6725,8 @@ e1550006
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 e1a07003
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@@ -6780,8 +6780,8 @@ e2433001
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 e1a00006
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 e92d4ef0
 e3a03000
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@@ -6898,12 +6898,12 @@ ebfff704
 eaffff9e
 e28dd00c
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 e59f1000
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 e3a05001
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@@ -6931,10 +6931,10 @@ e3550000
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 e20000ff
 e2402030
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@@ -7221,15 +7221,15 @@ e59f0024
 e1a0f00e
 e59f0020
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 e52de004
 e59f2038
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@@ -7247,10 +7247,10 @@ e88d5000
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 e20110ff
 e1a00001
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@@ -7259,7 +7259,7 @@ e59f6044
 e1a05001
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@@ -7287,7 +7287,7 @@ e3500000
 1afffff9
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@@ -7339,8 +7339,8 @@ e3500000
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@@ -7404,7 +7404,7 @@ e3e00003
 ea000065
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@@ -7506,13 +7506,13 @@ e3500000
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@@ -7671,7 +7671,7 @@ e3530000
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 e28dd004
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@@ -7735,7 +7735,7 @@ e2466001
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 e5941428
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@@ -7755,22 +7755,22 @@ e58a5000
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 e52de004
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@@ -7789,7 +7789,7 @@ e1520001
 bafffff5
 e1a0000c
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 e92d4010
 e59f40f0
 e1a0e002
@@ -7853,7 +7853,7 @@ e0230420
 1afffff8
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@@ -7870,11 +7870,11 @@ e1500003
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@@ -7884,7 +7884,7 @@ e0633004
 e3a0200a
 e0201293
 e1a01006
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 e3500009
 e1a04000
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@@ -7902,17 +7902,17 @@ e1a02007
 e8bd44f0
 eafff294
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 e92d4ef0
 e24dd048
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@@ -7925,13 +7925,13 @@ e1a09003
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 e1a06000
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@@ -8003,12 +8003,12 @@ e3590000
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@@ -8089,12 +8089,12 @@ eb0006dd
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 00107e84
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@@ -8437,7 +8437,7 @@ e2506000
 0bfff07e
 e1a00006
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@@ -8622,7 +8622,7 @@ e59f3008
 e5830000
 e1a00004
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@@ -8821,7 +8821,7 @@ e3540000
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@@ -8933,12 +8933,12 @@ e3570000
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@@ -9028,8 +9028,8 @@ e2822001
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 e28dd054
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@@ -9041,12 +9041,12 @@ ebffee17
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 ebffeea3
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@@ -9328,7 +9328,7 @@ e0690007
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 e28dd010
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@@ -9348,8 +9348,8 @@ e5830000
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 e0830180
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 e92d4030
 e1a05001
@@ -10136,11 +10136,11 @@ e0855004
 e0816006
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 e59f1024
 e1a04000
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@@ -10425,7 +10425,7 @@ ea000713
 e5940004
 e3a0101f
 e0820400
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 e3500000
 03a03002
 05843000
@@ -11376,36 +11376,36 @@ e201100f
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 e5503001
 e24bb001
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@@ -12265,9 +12265,15 @@ e1a0f00e
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 ea000001
 e2800001
 ee003510
@@ -12286,10 +12292,10 @@ e3a009e1
 e1a0f00e
 e52de004
 e59f0008
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 e3a00000
 e49df004
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 e1a0f00e
 e3a00000
 e3a01000
@@ -12313,11 +12319,11 @@ e3a00000
 e1a0f00e
 e52de004
 e59f0004
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 eafffffe
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 e52de004
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 ee113f10
 e3c33a01
 ee013f10
@@ -12326,10 +12332,12 @@ e3a00000
 e49df004
 e52de004
 e59f0008
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 e3a00000
 e49df004
-0010f9ec
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 00000000
 00000000
 00000000
@@ -12567,7 +12575,7 @@ e1a04000
 e59f0198
 e1a0a003
 e5976014
-ebffdc7e
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 e3540000
 13540080
 e1a05000
@@ -12576,16 +12584,16 @@ e1a05000
 1a00005b
 e59f0174
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 e3500000
 0a000006
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 e1a01000
 e59f0150
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 e59f3148
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@@ -12623,7 +12631,7 @@ e3530000
 e59f30d4
 e1a00005
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 e280000d
 e1a00120
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@@ -12631,7 +12639,7 @@ e59f40b4
 e5940000
 e1a01005
 e2800008
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 e5932000
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@@ -12659,8 +12667,8 @@ e3a04000
 e5834000
 e5834004
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 e1a00004
 e1a01006
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@@ -12668,39 +12676,35 @@ e1a0e00f
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 e3a00001
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 00000000
-0010cf8c
-0010cf94
-0010cf9c
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 0010cfac
 0010cfb4
 0010cfbc
@@ -12729,6 +12733,10 @@ eaffcf97
 0010d074
 0010d07c
 0010d084
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 00002580
 00004b00
 00009600
@@ -16015,9 +16023,9 @@ c30c8ea1
 6c656e72
 2e2e2e20
 ff000a0a
-0010c098
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 0010795c
-0010bff8
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 00105c34
 001004e8
 0010bf98
@@ -16031,7 +16039,7 @@ ff000a0a
 00100e64
 00000000
 00000000
-0010c44c
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 00000000
 00000000
 00000000
@@ -16045,85 +16053,77 @@ ff000a0a
 00000000
 00000000
 00100e18
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 00000000
 00000001
 00000001
-0010e334
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 00000000
 00000001
 00000002
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 00000000
 00000001
 00000020
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 00000000
 00000001
 00000010
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 00000000
 00000001
 00000040
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 00000000
 00000001
 00000080
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 00000002
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 00000003
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 00000000
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 00000000
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 00000001
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 00000001
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 00000040
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 00020000
 00020000
 00000000
 00000000
-0010fbd0
-0010fbd0
-0010fbd8
-0010fbd8
-0010fbe0
-0010fbe0
-0010fbe8
-0010fbe8
 0010fbf0
 0010fbf0
 0010fbf8
@@ -16372,6 +16372,14 @@ ff000a0a
 0010ffc0
 0010ffc8
 0010ffc8
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 ffffffff
 64756162
 65746172
@@ -16379,141 +16387,141 @@ ffffffff
 00303032
 00000000
 00000000
-0010d08c
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 00000002
-0010f238
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 00000001
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 0010f274
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 ffffffff
-0010e334
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 00000000
 00000000
-0010f284
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 00000007
-0010f294
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 0010f2b4
 0010f2c0
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-00000001
 0010f328
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 0010f348
-0010f350
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 ffffffff
-0010e334
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 00000000
 00000000
-0010f364
-00000001
-0010f374
-0010f37c
-00000002
 0010f384
-0010f388
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 0010f3ac
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 0010f3d4
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 00000006
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 0000000d
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 0010f464
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 0010f474
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 0010f494
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 ffffffff
-0010e334
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 00000000
 00000000
-0010f49c
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 00000005
-0010f4a8
-0010f4b0
-00000002
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-0010f4c0
-00000012
 0010f4c8
 0010f4d0
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 0010f4d8
 0010f4e0
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 ffffffff
-0010e334
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 00082008
 20202020
 20202020
 00000000
-0010f960
-0010f968
-0010e334
-0010f974
 0010f980
-0010f990
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 0010f9b0
-0010e334
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 00000003
 00000004
 00000005
@@ -16701,189 +16709,189 @@ ffffffff
 10020202
 02020202
 02020202
-0010d144
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 00000002
 00000000
 00100d00
-0010d14c
-0010d170
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 00000010
 00000001
 00100d60
-0010d220
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 00000001
 00000000
-0010c064
-0010d2b4
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 00000000
-0010d6d8
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 00000010
 00000001
 001016e0
-0010d6e0
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 00000003
 00000001
 00101904
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 00000002
 00000001
 001019cc
-0010d994
-0010d9c0
-0010da30
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 00000003
 00000000
 001019d4
-0010da38
 0010da58
-0010db80
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 00000004
 00000000
 001019dc
-0010db88
-0010dbbc
-0010dedc
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 00000004
 00000000
 00101c84
-0010dee4
-0010df14
-0010e16c
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 00000002
 00000000
 001028a4
-0010e174
-0010e1a4
-0010e1ec
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+0010e1c4
+0010e20c
 00000003
 00000000
 00102240
-0010e1f4
-0010e230
-0010df74
+0010e214
+0010e250
+0010df94
 00000003
 00000000
 00102240
-0010e290
-0010e230
-0010e498
+0010e2b0
+0010e250
+0010e4b8
 00000003
 00000001
 001033bc
-0010e49c
-0010e4b4
-0010e4f0
+0010e4bc
+0010e4d4
+0010e510
 00000002
 00000001
 00103394
-0010e4f4
-0010e51c
-0010e560
+0010e514
+0010e53c
+0010e580
 00000002
 00000001
 0010336c
-0010e564
-0010e58c
-0010e5d0
+0010e584
+0010e5ac
+0010e5f0
 00000004
 00000001
 0010311c
-0010e5d4
-0010e5f0
-0010e624
+0010e5f4
+0010e610
+0010e644
 00000004
 00000001
 00102e90
-0010e628
-0010e63c
-0010e670
+0010e648
+0010e65c
+0010e690
 00000004
 00000001
 00102f70
-0010e674
-0010e68c
-0010e6c4
+0010e694
+0010e6ac
+0010e6e4
 00000004
 00000001
 00102bbc
-0010e6cc
 0010e6ec
-0010e730
+0010e70c
+0010e750
 00000002
 00000001
 00102b78
-0010e738
-0010e75c
-0010e7cc
+0010e758
+0010e77c
+0010e7ec
 00000003
 00000001
 00102d98
-0010e7d4
-0010e7fc
-0010e848
+0010e7f4
+0010e81c
+0010e868
 00000004
 00000001
 00102c74
-0010e850
-0010e86c
-0010e8a8
+0010e870
+0010e88c
+0010e8c8
 00000002
 00000001
 001034c0
-0010e8b0
-0010e8dc
-0010ea24
+0010e8d0
+0010e8fc
+0010ea44
 00000010
 00000001
 00103bf8
-0010ea30
-0010ea58
-0010e9d0
+0010ea50
+0010ea78
+0010e9f0
 00000010
 00000000
 00103b70
-0010ead0
-0010eaf8
-0010eb74
+0010eaf0
+0010eb18
+0010eb94
 00000010
 00000001
 001068a4
-0010eb78
-0010ebac
-0010ec98
+0010eb98
+0010ebcc
+0010ecb8
 00000004
 00000001
 00103d74
-0010eca4
-0010ecd0
-0010eda0
+0010ecc4
+0010ecf0
+0010edc0
 00000001
 00000001
 00104310
-0010eda8
+0010edc8
 00000000
-0010edcc
+0010edec
 00000010
 00000001
 001040e8
-0010edd4
 0010edf4
-0010ee30
+0010ee14
+0010ee50
 00000010
 00000001
 00104168
-0010ee38
 0010ee58
-0010ef88
+0010ee78
+0010efa8
 00000010
 00000001
 00104168
-0010ef8c
+0010efac
 00000000
-- 
2.39.2


From 90bdd4a8174c0c08e132836696b5961c921b3206 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 00:56:31 -0500
Subject: [PATCH 06/16] Add a BigBlockRAM that's 8MB (and obviously not very
 synthesizable).  Make system use it on verilator.

---
 BigBlockRAM.v | 41 +++++++++++++++++++++++++++++++++++++++++
 system.v      |  7 ++++++-
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 BigBlockRAM.v

diff --git a/BigBlockRAM.v b/BigBlockRAM.v
new file mode 100644
index 0000000..b8ccbff
--- /dev/null
+++ b/BigBlockRAM.v
@@ -0,0 +1,41 @@
+module BigBlockRAM(
+	input clk,
+	input [31:0] bus_addr,
+	output wire [31:0] bus_rdata,
+	input [31:0] bus_wdata,
+	input bus_rd,
+	input bus_wr,
+	output wire bus_ready
+	);
+	
+	/* This module is mapped in physical memory from 0x00000000 to
+	 * 0x00800000.  rdata and ready must be driven to zero if the
+	 * address is not within the range of this module.
+	 */
+	wire decode = bus_addr[31:23] == 9'b0;
+	wire [22:0] ramaddr = {bus_addr[22:2], 2'b0};	/* mask off lower two bits
+							 * for word alignment */
+
+	reg [31:0] data [((8*1024*1024) / 4 - 1):0];
+	
+	reg [31:0] temprdata = 0;
+	reg [22:0] lastread = 23'h7FFFFFFF;
+	assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
+	
+	assign bus_ready = decode &&
+		(bus_wr || (bus_rd && (lastread == ramaddr)));
+	
+	initial
+		$readmemh("ram.hex", data);
+	
+	always @(posedge clk)
+	begin
+		if (bus_wr && decode)
+			data[ramaddr[22:2]] = bus_wdata;
+		
+		/* This is not allowed to be conditional -- stupid Xilinx
+		 * blockram. */
+		temprdata <= data[ramaddr[22:2]];
+		lastread <= ramaddr;
+	end
+endmodule
diff --git a/system.v b/system.v
index 1741203..07adfd8 100644
--- a/system.v
+++ b/system.v
@@ -127,7 +127,12 @@ module System(input clk);
 		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
 		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
 
-	BlockRAM blockram(
+`ifdef verilator
+	BigBlockRAM
+`else
+	BlockRAM
+`endif
+	blockram(
 		.clk(clk),
 		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
 		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
-- 
2.39.2


From 74b05f6e1ac2a7e14772c4bc2b8700208797f1ed Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 03:13:53 -0500
Subject: [PATCH 07/16] Decode: De-UNOPTFLAT it.

---
 Decode.v | 128 ++++++++++++++++++++++++++++---------------------------
 1 file changed, 65 insertions(+), 63 deletions(-)

diff --git a/Decode.v b/Decode.v
index 2c22746..3eecd55 100644
--- a/Decode.v
+++ b/Decode.v
@@ -80,6 +80,69 @@ module Decode(
 		read_1 = 4'hx;
 		read_2 = 4'hx;
 		
+		casez (insn)
+		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+		begin
+			read_0 = insn[15:12]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[11:8];  /* Rs */
+		end
+		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
+		begin end
+		`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
+			read_0 = insn[3:0];	/* Rm */
+		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
+			read_0 = insn[3:0];	/* Rm */
+		`DECODE_ALU_SWP:	/* Atomic swap */
+		begin
+			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+		end
+		`DECODE_ALU_BX:		/* Branch and exchange */
+			read_0 = insn[3:0];   /* Rn */
+		`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
+		begin
+			read_0 = insn[19:16];
+			read_1 = insn[3:0];
+			read_2 = insn[15:12];
+		end
+		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
+		begin
+			read_0 = insn[19:16];
+			read_1 = insn[15:12];
+		end
+		`DECODE_ALU:		/* ALU */
+		begin
+			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[11:8];  /* Rs for shift */
+		end
+		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
+		begin end
+		`DECODE_LDRSTR:		/* Single data transfer */
+		begin
+			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[15:12];
+		end
+		`DECODE_LDMSTM:		/* Block data transfer */
+			read_0 = insn[19:16];
+		`DECODE_BRANCH:		/* Branch */
+		begin end
+		`DECODE_LDCSTC:		/* Coprocessor data transfer */
+			read_0 = insn[19:16];
+		`DECODE_CDP:		/* Coprocessor data op */
+		begin end
+		`DECODE_MRCMCR:		/* Coprocessor register transfer */
+			read_0 = insn[15:12];
+		`DECODE_SWI:		/* SWI */
+		begin end
+		default:
+			$display("Undecoded instruction");
+		endcase
+	end
+	
+	always @(*) begin
 		op0_out = 32'hxxxxxxxx;
 		op1_out = 32'hxxxxxxxx;
 		op2_out = 32'hxxxxxxxx;
@@ -88,79 +151,41 @@ module Decode(
 		casez (insn)
 		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 		begin
-			read_0 = insn[15:12]; /* Rn */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = insn[11:8];  /* Rs */
-			
 			op0_out = regs0;
 			op1_out = regs1;
 			op2_out = regs2;
 		end
-//		`DECODE_ALU_MUL_LONG:	/* Multiply long */
-//		begin
-//			read_0 = insn[11:8]; /* Rn */
-//			read_1 = insn[3:0];   /* Rm */
-//			read_2 = 4'b0;       /* anyus */
-//
-//			op1_res = regs1;
-//		end
 		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
 		begin end
 		`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
-		begin
-			read_0 = insn[3:0];	/* Rm */
-			
 			op0_out = regs0;
-		end
 		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
-		begin
-			read_0 = insn[3:0];	/* Rm */
-			
 			if(insn[25]) begin     /* the constant case */
 				op0_out = rotate_res;
 			end else begin
 				op0_out = regs0;
 			end
-		end
 		`DECODE_ALU_SWP:	/* Atomic swap */
 		begin
-			read_0 = insn[19:16]; /* Rn */
-			read_1 = insn[3:0];   /* Rm */
-			
 			op0_out = regs0;
 			op1_out = regs1;
 		end
 		`DECODE_ALU_BX:		/* Branch and exchange */
-		begin
-			read_0 = insn[3:0];   /* Rn */
-			
 			op0_out = regs0;
-		end
 		`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
 		begin
-			read_0 = insn[19:16];
-			read_1 = insn[3:0];
-			read_2 = insn[15:12];
-
 			op0_out = regs0;
 			op1_out = regs1;
 			op2_out = regs2;
 		end
 		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
 		begin
-			read_0 = insn[19:16];
-			read_1 = insn[15:12];
-			
 			op0_out = regs0;
 			op1_out = {24'b0, insn[11:8], insn[3:0]};
 			op2_out = regs1;
 		end
 		`DECODE_ALU:		/* ALU */
 		begin
-			read_0 = insn[19:16]; /* Rn */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = insn[11:8];  /* Rs for shift */
-			
 			op0_out = regs0;
 			if(insn[25]) begin     /* the constant case */
 				carry_out = incpsr[`CPSR_C];
@@ -170,16 +195,8 @@ module Decode(
 				op1_out = shift_res;
 			end
 		end
-		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
-		begin
-			/* eat shit */
-		end
 		`DECODE_LDRSTR:		/* Single data transfer */
 		begin
-			read_0 = insn[19:16]; /* Rn */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = insn[15:12];
-			
 			op0_out = regs0;
 			if(!insn[25] /* immediate */) begin
 				op1_out = {20'b0, insn[11:0]};
@@ -192,39 +209,24 @@ module Decode(
 		end
 		`DECODE_LDMSTM:		/* Block data transfer */
 		begin
-			read_0 = insn[19:16];
-			
 			op0_out = regs0;
 			op1_out = {16'b0, insn[15:0]};
 		end
 		`DECODE_BRANCH:		/* Branch */
-		begin
 			op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
-		end
 		`DECODE_LDCSTC:		/* Coprocessor data transfer */
 		begin
-			read_0 = insn[19:16];
-			
 			op0_out = regs0;
 			op1_out = {24'b0, insn[7:0]};
 		end
 		`DECODE_CDP:		/* Coprocessor data op */
-		begin
-		end
+		begin end
 		`DECODE_MRCMCR:		/* Coprocessor register transfer */
-		begin
-			read_0 = insn[15:12];
-			
 			op0_out = regs0;
-		end
 		`DECODE_SWI:		/* SWI */
-		begin
-		end
-		default:
-			$display("Undecoded instruction");
+		begin end
 		endcase
 	end
-
 	
 	always @ (posedge clk) begin
 		if (!stall)
-- 
2.39.2


From 3ccca00960e338365e7ce4ce57af1ec019117212 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 03:44:25 -0500
Subject: [PATCH 08/16] Execute: Split things out into their own always blocks
 there, too.

---
 Execute.v | 124 ++++++++++++++++++++++++++++++++++++------------------
 1 file changed, 83 insertions(+), 41 deletions(-)

diff --git a/Execute.v b/Execute.v
index ac446aa..c1049ba 100644
--- a/Execute.v
+++ b/Execute.v
@@ -89,51 +89,45 @@ module Execute(
 	reg prevstall = 0;
 	always @(posedge clk)
 		prevstall <= outstall;
-
+	
 	always @(*)
 	begin
 		outstall = stall;
-		next_outbubble = inbubble | flush | delayedflush;
+		
+		casez (insn)
+		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+			outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
+		endcase
+	end
+	
+	/* ALU inputs */
+	always @(*)
+	begin
+		alu_in0 = op0;
+		alu_in1 = op1;
+		alu_op = insn[24:21];
+		alu_setflags = insn[20] /* S */;
+	end
+	
+	/* Register outputs */
+	always @(*)
+	begin
 		next_outcpsr = cpsr;
 		next_outspsr = spsr;
 		next_outcpsrup = 0;
 		next_write_reg = 0;
 		next_write_num = 4'hx;
 		next_write_data = 32'hxxxxxxxx;
-
-		mult_start = 0;
-		mult_acc0 = 32'hxxxxxxxx;
-		mult_in0 = 32'hxxxxxxxx;
-		mult_in1 = 32'hxxxxxxxx;
-
-		alu_in0 = 32'hxxxxxxxx;
-		alu_in1 = 32'hxxxxxxxx;
-		alu_op = 4'hx;	/* hax! */
-		alu_setflags = 1'bx;
-
-		jmp = 1'b0;
-		jmppc = 32'h00000000;
-
-		casez (insn)
+		
+		casez(insn)
 		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 		begin
-			if (!prevstall && !inbubble)
-			begin
-				mult_start = 1;
-				mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
-				mult_in0 = op1 /* Rm */;
-				mult_in1 = op2 /* Rs */;
-				$display("New MUL instruction");
-			end
-			outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
-			next_outbubble = next_outbubble | !mult_done | !prevstall;
 			next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 			next_outcpsrup = insn[20] /* S */;
 			next_write_reg = 1;
 			next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
 			next_write_data = mult_result;
 		end
-//		`DECODE_ALU_MUL_LONG,	/* Multiply long */
 		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
 		begin
 			next_write_reg = 1;
@@ -142,7 +136,6 @@ module Execute(
 				next_write_data = spsr;
 			else
 				next_write_data = cpsr;
-			next_outcpsrup = 1;
 		end
 		`DECODE_ALU_MSR,	/* MSR (Transfer register to PSR) */
 		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
@@ -168,33 +161,82 @@ module Execute(
 		begin end
 		`DECODE_ALU:		/* ALU */
 		begin
-			alu_in0 = op0;
-			alu_in1 = op1;
-			alu_op = insn[24:21];
-			alu_setflags = insn[20] /* S */;
-			
 			if (alu_setres) begin
 				next_write_reg = 1;
 				next_write_num = insn[15:12] /* Rd */;
 				next_write_data = alu_result;
 			end
 			
-			next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
-			next_outcpsrup = insn[20] /* S */;
+			if (insn[20] /* S */) begin
+				next_outcpsrup = 1;
+				next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
+			end
 		end
 		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
 		`DECODE_LDRSTR,		/* Single data transfer */
 		`DECODE_LDMSTM:		/* Block data transfer */
 		begin end
+		`DECODE_BRANCH:		/* Branch */
+		begin
+			if(insn[24] /* L */) begin
+				next_write_reg = 1;
+				next_write_num = 4'hE; /* link register */
+				next_write_data = pc + 32'h4;
+			end
+		end
+		endcase
+	end
+	
+	/* Multiplier inputs */
+	always @(*)
+	begin
+		mult_start = 0;
+		mult_acc0 = 32'hxxxxxxxx;
+		mult_in0 = 32'hxxxxxxxx;
+		mult_in1 = 32'hxxxxxxxx;
+		
+		casez(insn)
+		`DECODE_ALU_MULT:
+		begin
+			if (!prevstall /* i.e., this is a new one */ && !inbubble /* i.e., this is a real one */)
+			begin
+				mult_start = 1;
+				mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
+				mult_in0 = op1 /* Rm */;
+				mult_in1 = op2 /* Rs */;
+				$display("New MUL instruction");
+			end
+		end
+		endcase
+	end
+
+	/* Miscellaneous cleanup. */
+	always @(*)
+	begin
+		next_outbubble = inbubble | flush | delayedflush;
+
+		jmp = 1'b0;
+		jmppc = 32'h00000000;
+
+		casez (insn)
+		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+			next_outbubble = next_outbubble | !mult_done | !prevstall;
+		`DECODE_ALU_MRS,	/* MRS (Transfer PSR to register) */
+		`DECODE_ALU_MSR,	/* MSR (Transfer register to PSR) */
+		`DECODE_ALU_MSR_FLAGS,	/* MSR (Transfer register or immediate to PSR, flag bits only) */
+		`DECODE_ALU_SWP,	/* Atomic swap */
+		`DECODE_ALU_BX,		/* Branch */
+		`DECODE_ALU_HDATA_REG,	/* Halfword transfer - register offset */
+		`DECODE_ALU_HDATA_IMM,	/* Halfword transfer - immediate offset */
+		`DECODE_ALU,		/* ALU */
+		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
+		`DECODE_LDRSTR,		/* Single data transfer */
+		`DECODE_LDMSTM:		/* Block data transfer */
+		begin end
 		`DECODE_BRANCH:
 		begin
 			if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
 				jmppc = pc + op0 + 32'h8;
-				if(insn[24]) begin
-					next_write_reg = 1;
-					next_write_num = 4'hE; /* link register */
-					next_write_data = pc + 32'h4;
-				end
 				jmp = 1'b1;
 			end
 		end                     /* Branch */
-- 
2.39.2


From 8b09558c6aa1ac41a28e9a16d5764df5af5704ee Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 03:46:00 -0500
Subject: [PATCH 09/16] BigBlockRAM: Remove excess F.

---
 BigBlockRAM.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BigBlockRAM.v b/BigBlockRAM.v
index b8ccbff..7e6ea99 100644
--- a/BigBlockRAM.v
+++ b/BigBlockRAM.v
@@ -19,7 +19,7 @@ module BigBlockRAM(
 	reg [31:0] data [((8*1024*1024) / 4 - 1):0];
 	
 	reg [31:0] temprdata = 0;
-	reg [22:0] lastread = 23'h7FFFFFFF;
+	reg [22:0] lastread = 23'h7FFFFF;
 	assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
 	
 	assign bus_ready = decode &&
-- 
2.39.2


From ac760abbb074404374f0b376981d5b1c695ac9b3 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 03:56:01 -0500
Subject: [PATCH 10/16] DCache, ICache: Move curdata out to its own wire for
 synthesis.  Fix up a blocking assign that should be a nonblocking assign.

---
 DCache.v | 5 +++--
 ICache.v | 7 ++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/DCache.v b/DCache.v
index ccaa6b1..f4dff5a 100644
--- a/DCache.v
+++ b/DCache.v
@@ -48,9 +48,10 @@ module DCache(
 	
 	wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
 	
+	wire [31:0] curdata = cache_data[idx][didx_word];
 	always @(*) begin
 		rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
-		rd_data = cache_data[idx][didx_word];
+		rd_data = curdata;
 		if (!rw_wait && rd_req)
 			$display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
 	end
@@ -90,6 +91,6 @@ module DCache(
 					cache_valid[idx] <= 0;
 			end
 		end else if (wr_req && cache_hit)
-			cache_data[idx][addr[5:2]] = wr_data;
+			cache_data[idx][addr[5:2]] <= wr_data;
 	end
 endmodule
diff --git a/ICache.v b/ICache.v
index d9fbf04..e6754b7 100644
--- a/ICache.v
+++ b/ICache.v
@@ -48,10 +48,11 @@ module ICache(
 	reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
 	
 	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
-	
-	always @(*) begin	/* XXX does this work nowadays? */
+
+	wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
+	always @(*) begin
 		rd_wait = rd_req && !cache_hit;
-		rd_data = cache_data[rd_idx][rd_didx_word];
+		rd_data = curdata;
 	end
 	
 	reg [3:0] cache_fill_pos = 0;
-- 
2.39.2


From f5f16509c3105f1dc274f61c66317f3926463695 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 04:18:39 -0500
Subject: [PATCH 11/16] RegFile: Move to assigns, since XST can't always
 @(regfile).

---
 RegFile.v | 39 ++++++++++-----------------------------
 1 file changed, 10 insertions(+), 29 deletions(-)

diff --git a/RegFile.v b/RegFile.v
index 730a620..c0e5abd 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,14 +1,14 @@
 module RegFile(
 	input clk,
 	input [3:0] read_0,
-	output reg [31:0] rdata_0,
+	output wire [31:0] rdata_0,
 	input [3:0] read_1,
-	output reg [31:0] rdata_1,
+	output wire [31:0] rdata_1,
 	input [3:0] read_2,
-	output reg [31:0] rdata_2,
+	output wire [31:0] rdata_2,
 	input [3:0] read_3,
-	output reg [31:0] rdata_3,
-	output reg [31:0] spsr,
+	output wire [31:0] rdata_3,
+	output wire [31:0] spsr,
 	input write,
 	input [3:0] write_reg,
 	input [31:0] write_data
@@ -35,30 +35,11 @@ module RegFile(
 		regfile[4'hF] = 32'h00000000;	/* Start off claiming we are in user mode. */
 	end
 	
-	always @(*)
-	begin
-		if ((read_0 == write_reg) && write)
-			rdata_0 = write_data;
-		else
-			rdata_0 = regfile[read_0];
-		
-		if ((read_1 == write_reg) && write)
-			rdata_1 = write_data;
-		else
-			rdata_1 = regfile[read_1];
-		
-		if ((read_2 == write_reg) && write)
-			rdata_2 = write_data;
-		else
-			rdata_2 = regfile[read_2];
-
-		if ((read_3 == write_reg) && write)
-			rdata_3 = write_data;
-		else
-			rdata_3 = regfile[read_3];
-		
-		spsr = regfile[4'hF];
-	end
+	assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0];
+	assign rdata_1 = ((read_1 == write_reg) && write) ? write_data : regfile[read_1];
+	assign rdata_2 = ((read_2 == write_reg) && write) ? write_data : regfile[read_2];
+	assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3];
+	assign spsr = regfile[4'hF];
 	
 	always @(posedge clk)
 		if (write)
-- 
2.39.2


From dfddccfb552a24c60589696269a5325ec267c46d Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 04:18:58 -0500
Subject: [PATCH 12/16] Issue: Use wires, since again XST can't always
 @(cpsr_inflight).

---
 Issue.v | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/Issue.v b/Issue.v
index 792fdbd..153f25f 100644
--- a/Issue.v
+++ b/Issue.v
@@ -12,7 +12,7 @@ module Issue(
 	input [31:0] inpc,
 	input [31:0] cpsr,
 	
-	output reg outstall = 0,	/* stage outputs */
+	output wire outstall,	/* stage outputs */
 	output reg outbubble = 1,
 	output reg [31:0] outpc = 0,
 	output reg [31:0] outinsn = 0
@@ -265,10 +265,6 @@ module Issue(
 	reg cpsr_inflight [1:0];
 	reg [15:0] regs_inflight [1:0];
 	
-	reg waiting_cpsr;
-	reg waiting_regs;
-	wire waiting = waiting_cpsr | waiting_regs;
-	
 	initial
 	begin
 		cpsr_inflight[0] = 0;
@@ -276,14 +272,11 @@ module Issue(
 		regs_inflight[0] = 0;
 		regs_inflight[1] = 0;
 	end
-		
-	always @(*)
-	begin
-		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
-		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
-		
-		outstall = (waiting && !inbubble && !flush) || stall;	/* Happens in an always @*, because it is an exception. */
-	end
+	
+	wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
+	wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+	wire waiting = waiting_cpsr | waiting_regs;
+	assign outstall = (waiting && !inbubble && !flush) || stall;
 
 	reg delayedflush = 0;
 	always @(posedge clk)
-- 
2.39.2


From d43b0ab9a916f24601dd987fa84eb6e629b1679d Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 04:31:18 -0500
Subject: [PATCH 13/16] Fetch: Fix async reset to actually not do it wrong.

---
 Fetch.v | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/Fetch.v b/Fetch.v
index 918e53c..aa9bd7c 100644
--- a/Fetch.v
+++ b/Fetch.v
@@ -16,8 +16,10 @@ module Fetch(
 	
 	reg qjmp = 0;	/* A jump has been queued up while we were waiting. */
 	reg [31:0] qjmppc;
-	always @(posedge clk)
-		if ((rd_wait || stall) && jmp)
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst)
+			qjmp <= 0;
+		else if ((rd_wait || stall) && jmp)
 			{qjmp,qjmppc} <= {jmp, jmppc};
 		else if (!rd_wait && !stall && qjmp)	/* It has already been intoed. */
 			{qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
@@ -36,18 +38,10 @@ module Fetch(
 	assign rd_addr = reqpc;
 	assign rd_req = 1;
 	
-	always @(negedge Nrst)
-	begin
-		pc <= 32'hFFFFFFFC;
-		qjmp <= 0;
-		bubble <= 1;
-	end
-	
-	always @(posedge clk)
+	always @(posedge clk or negedge Nrst)
 	begin
 		if (!Nrst) begin
 			pc <= 32'hFFFFFFFC;
-			qjmp <= 0;
 			bubble <= 1;
 		end else if (!stall)
 		begin
-- 
2.39.2


From fd003c7a793fb17fb6dc7ba52873b883b28a578b Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 05:08:28 -0500
Subject: [PATCH 14/16] System, Terminal: Provide real-world outputs on
 non-Verilator to avoid optimizing the whole system to nothing.

---
 Terminal.v | 20 +++++++++++++++++++-
 system.v   | 17 +++++++++++++++--
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/Terminal.v b/Terminal.v
index dd041d0..9ddd5d3 100644
--- a/Terminal.v
+++ b/Terminal.v
@@ -7,7 +7,14 @@ module Terminal(
 	output reg cp_busy,
 	input cp_rnw,
 	output reg [31:0] cp_read = 0,
-	input [31:0] cp_write);
+	input [31:0] cp_write
+`ifdef verilator
+`else
+	, output reg [8:0] sys_odata = 0,
+	input [8:0] sys_idata,
+	output reg sys_tookdata = 0
+`endif
+);
 	
 	/* Terminal pretends to be cp5. */
 	reg towrite = 0;
@@ -41,5 +48,16 @@ module Terminal(
 			$c("{extern void term_output(unsigned char d); term_output(",data,");}");
 		else if (didread || !indata[8])
 			indata = $c("({extern unsigned int term_input(); term_input();})");
+`else
+	always @(posedge clk)
+	begin
+		sys_odata = {towrite,data};
+		if (didread || !indata[8])
+		begin
+			indata = sys_idata;
+			sys_tookdata = 1;
+		end else
+			sys_tookdata = 0;
+	end
 `endif
 endmodule
diff --git a/system.v b/system.v
index 07adfd8..f134ffc 100644
--- a/system.v
+++ b/system.v
@@ -1,7 +1,15 @@
 `define BUS_ICACHE 1
 `define BUS_DCACHE 0
 
-module System(input clk);
+module System(input clk
+`ifdef verilator
+`else
+	, output wire [8:0] sys_odata,
+	input [8:0] sys_idata,
+	output wire sys_tookdata
+`endif
+	);
+	
 	wire [7:0] bus_req;
 	wire [7:0] bus_ack;
 	wire [31:0] bus_addr;
@@ -208,7 +216,12 @@ module System(input clk);
 	Terminal terminal(	
 		.clk(clk),
 		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
-		.cp_read(cp_read_terminal), .cp_write(cp_write));
+		.cp_read(cp_read_terminal), .cp_write(cp_write)
+`ifdef verilator
+`else
+		, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
+`endif
+		);
 	
 	Writeback writeback(
 		.clk(clk),
-- 
2.39.2


From 2b5c79c05898ff20b0c04cd78bccb2580f6c8331 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 05:37:43 -0500
Subject: [PATCH 15/16] DCache, ICache: Make cache_data a 1-D array to enable
 better synthesizability on Xilinx.

---
 BlockRAM.v |  4 ++--
 DCache.v   | 30 +++++++++++++++---------------
 ICache.v   | 36 +++++++++++++++++-------------------
 ram.hex    |  2 +-
 4 files changed, 35 insertions(+), 37 deletions(-)

diff --git a/BlockRAM.v b/BlockRAM.v
index e0eceeb..091c749 100644
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -31,11 +31,11 @@ module BlockRAM(
 	always @(posedge clk)
 	begin
 		if (bus_wr && decode)
-			data[ramaddr[13:2]] = bus_wdata;
+			data[ramaddr[13:2]] <= bus_wdata;
 		
 		/* This is not allowed to be conditional -- stupid Xilinx
 		 * blockram. */
-		temprdata <= data[ramaddr[13:2]];
+		temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
 		lastread <= ramaddr;
 	end
 endmodule
diff --git a/DCache.v b/DCache.v
index f4dff5a..aec6ae6 100644
--- a/DCache.v
+++ b/DCache.v
@@ -29,7 +29,7 @@ module DCache(
 	
 	reg cache_valid [15:0];
 	reg [21:0] cache_tags [15:0];
-	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	reg [31:0] cache_data [255:0 /* {line,word} */];
 
 	integer i;	
 	initial
@@ -48,7 +48,7 @@ module DCache(
 	
 	wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
 	
-	wire [31:0] curdata = cache_data[idx][didx_word];
+	wire [31:0] curdata = cache_data[{idx,didx_word}];
 	always @(*) begin
 		rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
 		rd_data = curdata;
@@ -79,18 +79,18 @@ module DCache(
 		prev_addr <= {addr[31:6], 6'b0};
 		if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
-		else if (rd_req && !cache_hit) begin
-			if (bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
-				$display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
-				cache_data[idx][cache_fill_pos] <= bus_rdata;
-				cache_fill_pos <= cache_fill_pos + 1;
-				if (cache_fill_pos == 15) begin	/* Done? */
-					cache_tags[idx] <= tag;
-					cache_valid[idx] <= 1;
-				end else
-					cache_valid[idx] <= 0;
-			end
-		end else if (wr_req && cache_hit)
-			cache_data[idx][addr[5:2]] <= wr_data;
+		else if (rd_req && !cache_hit && bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
+			$display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
+			cache_fill_pos <= cache_fill_pos + 1;
+			if (cache_fill_pos == 15) begin	/* Done? */
+				cache_tags[idx] <= tag;
+				cache_valid[idx] <= 1;
+			end else
+				cache_valid[idx] <= 0;
+		end
+		
+		/* Split this out because XST is kind of silly about this sort of thing. */
+		if ((rd_req && !cache_hit && bus_ready && bus_ack) || (wr_req && cache_hit))
+			cache_data[wr_req ? {idx,addr[5:2]} : {idx,cache_fill_pos}] <= wr_req ? wr_data : bus_rdata;
 	end
 endmodule
diff --git a/ICache.v b/ICache.v
index e6754b7..8b9eac3 100644
--- a/ICache.v
+++ b/ICache.v
@@ -30,7 +30,7 @@ module ICache(
 	
 	reg cache_valid [15:0];
 	reg [21:0] cache_tags [15:0];
-	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	reg [31:0] cache_data [255:0 /* {line, word} */];	//synthesis attribute ram_style of cache_data is distributed
 	
 	integer i;
 	initial
@@ -48,12 +48,6 @@ module ICache(
 	reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
 	
 	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
-
-	wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
-	always @(*) begin
-		rd_wait = rd_req && !cache_hit;
-		rd_data = curdata;
-	end
 	
 	reg [3:0] cache_fill_pos = 0;
 	assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
@@ -65,23 +59,27 @@ module ICache(
 			bus_addr = 0;
 			bus_rd = 0;
 		end
+
+	wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}];
+	always @(*) begin
+		rd_wait = rd_req && !cache_hit;
+		rd_data = curdata;
+	end
 	
 	always @(posedge clk) begin
 		prev_rd_addr <= {rd_addr[31:6], 6'b0};
 		if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
-		else if (rd_req && !cache_hit) begin
-			if (bus_ack && bus_ready) begin	/* Started the fill, and we have data. */
-				$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
-				cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
-				cache_fill_pos <= cache_fill_pos + 1;
-				if (cache_fill_pos == 15) begin	/* Done? */
-					cache_tags[rd_idx] <= rd_tag;
-					cache_valid[rd_idx] <= 1;
-					$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
-				end else
-					cache_valid[rd_idx] <= 0;
-			end
+		else if (rd_req && !cache_hit && bus_ack && bus_ready) begin
+			$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+			cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata;
+			cache_fill_pos <= cache_fill_pos + 1;
+			if (cache_fill_pos == 15) begin	/* Done? */
+				cache_tags[rd_idx] <= rd_tag;
+				cache_valid[rd_idx] <= 1;
+				$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
+			end else
+				cache_valid[rd_idx] <= 0;
 		end
 	end
 endmodule
diff --git a/ram.hex b/ram.hex
index 96b3cdf..6d0fcf5 120000
--- a/ram.hex
+++ b/ram.hex
@@ -1 +1 @@
-tests/u-boot.hex
\ No newline at end of file
+tests/testbench.hex
\ No newline at end of file
-- 
2.39.2


From cc1ce5b3e8f2d357106c2d3da355360f99c6c9c3 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 25 Jan 2009 03:39:09 -0500
Subject: [PATCH 16/16] Memory: Fix up a constant that was typoed and
 malformed.

---
 Memory.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Memory.v b/Memory.v
index eccddb2..5269f64 100644
--- a/Memory.v
+++ b/Memory.v
@@ -125,6 +125,7 @@ module Memory(
 		busaddr = 32'hxxxxxxxx;
 		data_size = 3'bxxx;
 		outstall = 1'b0;
+		st_read = 4'hx;
 		do_rd_data_latch = 0;
 		next_write_reg = write_reg;
 		next_write_num = write_num;
-- 
2.39.2