From c2b9d4b7fdabce17f5204750bad87635d5fa8a34 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Mon, 5 Jan 2009 04:21:39 -0500
Subject: [PATCH 01/16] you snipeer

---
 system.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/system.v b/system.v
index 736e6f2..4a485c3 100644
--- a/system.v
+++ b/system.v
@@ -54,6 +54,10 @@ module System(input clk);
 	wire [31:0] pc_out_fetch;
 	wire [31:0] pc_out_issue;
 
+	wire execute_outflush = jmp;
+	wire issue_flush = execute_outflush;
+	wire execute_flush = 1'b0;
+
 	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
 	ICache icache(
@@ -84,7 +88,7 @@ module System(input clk);
 	Issue issue(
 		.clk(clk),
 		.Nrst(1'b1 /* XXX */),
-		.stall(stall_cause_execute), .flush(1'b0 /* XXX */),
+		.stall(stall_cause_execute), .flush(issue_flush),
 		.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
 		.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
 		.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
@@ -106,7 +110,7 @@ module System(input clk);
 	
 	Execute execute(
 		.clk(clk), .Nrst(1'b0),
-		.stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
+		.stall(1'b0 /* XXX */), .flush(execute_flush),
 		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
 		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
 		.op2(decode_out_op2), .carry(decode_out_carry),
-- 
2.39.2


From 739fa95a4d31b541913db02b825c731ad3821430 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Mon, 5 Jan 2009 04:34:39 -0500
Subject: [PATCH 02/16] flush generate bubble, yes

---
 Issue.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Issue.v b/Issue.v
index ef53bc3..a6b7109 100644
--- a/Issue.v
+++ b/Issue.v
@@ -297,6 +297,7 @@ module Issue(
 			cpsr_inflight[1] = 1'b0;
 			regs_inflight[0] = 16'b0;
 			regs_inflight[1] = 16'b0;
+			outbubble <= 1'b1;
 		end
 		else if (!stall)
 		begin
@@ -305,7 +306,7 @@ module Issue(
 			regs_inflight[0] <= regs_inflight[1];
 			regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
 			
-			outbubble <= inbubble | waiting | !condition_met | flush;
+			outbubble <= inbubble | waiting | !condition_met;
 			outpc <= inpc;
 			outinsn <= insn;
 		end
-- 
2.39.2


From f8bf38caa402400c5063dc97da9e810c5d9d7ec5 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Mon, 5 Jan 2009 04:44:42 -0500
Subject: [PATCH 03/16] execute: do stuff only if bubble, still incorrect

---
 Execute.v | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/Execute.v b/Execute.v
index cefc4ef..4e3f44f 100644
--- a/Execute.v
+++ b/Execute.v
@@ -163,13 +163,15 @@ module Execute(
 		begin end
 		`DECODE_BRANCH:
 		begin
-			jmppc = pc + op0 + 32'h8;
-			if(insn[24]) begin
-				next_write_reg = 1;
-				next_write_num = 4'hE; /* link register */
-				next_write_data = pc + 32'h4;
+			if(!prevstall && !inbubble) begin
+				jmppc = pc + op0 + 32'h8;
+				if(insn[24]) begin
+					next_write_reg = 1;
+					next_write_num = 4'hE; /* link register */
+					next_write_data = pc + 32'h4;
+				end
+				jmp = 1'b1;
 			end
-			jmp = 1'b1;
 		end                     /* Branch */
 		`DECODE_LDCSTC,		/* Coprocessor data transfer */
 		`DECODE_CDP,		/* Coprocessor data op */
-- 
2.39.2


From 7947b9c731a2c981f1a32d2f8f47ab42464e7b17 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 5 Jan 2009 05:26:19 -0500
Subject: [PATCH 04/16] Ok, it work.

---
 Execute.v        | 8 ++++----
 Issue.v          | 2 +-
 ram.comments.hex | 4 ++--
 ram.hex          | 4 ++--
 system.v         | 9 ++++-----
 5 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/Execute.v b/Execute.v
index 4e3f44f..8a7d8f6 100644
--- a/Execute.v
+++ b/Execute.v
@@ -163,12 +163,12 @@ module Execute(
 		begin end
 		`DECODE_BRANCH:
 		begin
-			if(!prevstall && !inbubble) begin
+			if(!inbubble) begin
 				jmppc = pc + op0 + 32'h8;
 				if(insn[24]) begin
 					next_write_reg = 1;
 					next_write_num = 4'hE; /* link register */
-					next_write_data = pc + 32'h4;
+					next_write_data = pc - 32'h4;
 				end
 				jmp = 1'b1;
 			end
@@ -236,8 +236,8 @@ module ALU(
 	output reg [31:0] cpsr_out,
 	output reg setres
 );
-	wire [31:0] res;
-	wire flag_n, flag_z, flag_c, flag_v, setres;
+	reg [31:0] res;
+	reg flag_n, flag_z, flag_c, flag_v;
 	wire [32:0] sum, diff, rdiff;
 	wire sum_v, diff_v, rdiff_v;
 
diff --git a/Issue.v b/Issue.v
index a6b7109..7b281a3 100644
--- a/Issue.v
+++ b/Issue.v
@@ -282,7 +282,7 @@ module Issue(
 		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
 		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
 		
-		outstall = (waiting && !inbubble) || stall;	/* Happens in an always @*, because it is an exception. */
+		outstall = ((waiting && !inbubble) || stall) && !flush;	/* Happens in an always @*, because it is an exception. */
 	end
 	
 	/* Actually do the issue. */
diff --git a/ram.comments.hex b/ram.comments.hex
index bffc93b..b1fa950 100644
--- a/ram.comments.hex
+++ b/ram.comments.hex
@@ -26,9 +26,9 @@ E180F081
 E180F081
 E180F081
 EA000000 // jump forward
-EBFFFFFF // whirrr, skipped the first time
+EAFFFFFE // whirrr, skipped the first time
 E1A00000 // nop
-EBFFFFFD // jump back
+EBFFFFFC // jump back
 E0000000
 E0000000
 E0000000
diff --git a/ram.hex b/ram.hex
index 9f19cbb..1a068cc 100644
--- a/ram.hex
+++ b/ram.hex
@@ -21,9 +21,9 @@ E180F081
 E180F081
 E180F081
 EA000000
-EBFFFFFF
+EAFFFFFE
 E1A00000
-EAFFFFFD
+EBFFFFFC
 E0000000
 E0000000
 E0000000
diff --git a/system.v b/system.v
index f80f327..4601ae7 100644
--- a/system.v
+++ b/system.v
@@ -54,9 +54,7 @@ module System(input clk);
 	wire [31:0] pc_out_fetch;
 	wire [31:0] pc_out_issue;
 
-	wire execute_outflush = jmp;
-	wire issue_flush = execute_outflush;
-	wire execute_flush = 1'b0;
+	wire execute_out_backflush;
 
 	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
@@ -88,7 +86,7 @@ module System(input clk);
 	Issue issue(
 		.clk(clk),
 		.Nrst(1'b1 /* XXX */),
-		.stall(stall_cause_execute), .flush(issue_flush),
+		.stall(stall_cause_execute), .flush(execute_out_backflush),
 		.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
 		.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
 		.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
@@ -110,7 +108,7 @@ module System(input clk);
 	
 	Execute execute(
 		.clk(clk), .Nrst(1'b0),
-		.stall(1'b0 /* XXX */), .flush(execute_flush),
+		.stall(1'b0 /* XXX */), .flush(1'b0),
 		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
 		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
 		.op2(decode_out_op2), .carry(decode_out_carry),
@@ -119,6 +117,7 @@ module System(input clk);
 		.write_data(execute_out_write_data),
 		.jmppc(jmppc),
 		.jmp(jmp));
+	assign execute_out_backflush = jmp;
 
 	reg [31:0] clockno = 0;
 	always @(posedge clk)
-- 
2.39.2


From 6060e5359241449a70a27ed0d7023951ee21ceeb Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 5 Jan 2009 22:20:53 -0500
Subject: [PATCH 05/16] Add the DCache.

---
 DCache.v | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 DCache.v

diff --git a/DCache.v b/DCache.v
new file mode 100644
index 0000000..4528bd8
--- /dev/null
+++ b/DCache.v
@@ -0,0 +1,81 @@
+/* 16 cache entries, 64-byte long cache lines */
+
+module DCache(
+	input clk,
+	
+	/* ARM core interface */
+	input [31:0] addr,
+	input rd_req,
+	input wr_req,
+	output reg rw_wait,
+	input [31:0] wr_data,
+	output reg [31:0] rd_data,
+	
+	/* bus interface */
+	output wire bus_req,
+	input bus_ack,
+	output reg [31:0] bus_addr = 0,
+	input [31:0] bus_rdata,
+	output reg [31:0] bus_wdata,
+	output reg bus_rd = 0,
+	output reg bus_wr = 0,
+	input bus_ready);
+	
+	/* [31 tag 10] [9 cache index 6] [5 data index 0]
+	 * so the data index is 6 bits long
+	 * so the cache index is 4 bits long
+	 * so the tag is 22 bits long. c.c
+	 */
+	
+	reg cache_valid [15:0];
+	reg [21:0] cache_tags [15:0];
+	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	
+	reg [4:0] i;
+	initial
+		for (i = 0; i < 16; i = i + 1)
+		begin
+			cache_valid[i[3:0]] = 0;
+			cache_tags[i[3:0]] = 0;
+		end
+	
+	wire [5:0] didx = addr[5:0];
+	wire [3:0] didx_word = didx[5:2];
+	wire [3:0] idx = addr[9:6];
+	wire [21:0] tag = addr[31:10];
+	
+	wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
+	
+	always @(*) begin
+		rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
+		rd_data = cache_data[idx][didx_word];
+	end
+	
+	reg [3:0] cache_fill_pos = 0;
+	assign bus_req = (rd_req && !cache_hit) || wr_req;
+	always @(*)
+		if (rd_req && !cache_hit && bus_ack) begin
+			bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+			bus_rd = 1;
+		end else if (wr_req && bus_ack) begin
+			bus_addr = addr;
+			bus_wr = 1;
+			bus_wdata = wr_data;
+		end else begin
+			bus_addr = 0;
+			bus_rd = 0;
+		end
+	
+	always @(posedge clk)
+		if (rd_req && !cache_hit) begin
+			if (bus_ready) begin	/* Started the fill, and we have data. */
+				cache_data[idx][cache_fill_pos] <= bus_rdata;
+				cache_fill_pos <= cache_fill_pos + 1;
+				if (cache_fill_pos == 15) begin	/* Done? */
+					cache_tags[idx] <= tag;
+					cache_valid[idx] <= 1;
+				end
+			end
+		end else if (wr_req && cache_hit)
+			cache_data[idx][addr[5:2]] = wr_data;
+endmodule
-- 
2.39.2


From 2393422aab14e1b2172b4e52b9117272cc13c72e Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 5 Jan 2009 22:21:53 -0500
Subject: [PATCH 06/16] Execute.v: Add outpc and outinsn. System.v: Add and
 make wires consistent.

---
 Execute.v |  6 +++++-
 system.v  | 12 +++++++-----
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/Execute.v b/Execute.v
index 8a7d8f6..cd71d76 100644
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,9 @@ module Execute(
 	output reg [3:0] write_num = 4'bxxxx,
 	output reg [31:0] write_data = 32'hxxxxxxxx,
 	output reg [31:0] jmppc,
-	output reg jmp
+	output reg jmp,
+	output reg [31:0] outpc,
+	output reg [31:0] outinsn
 	);
 	
 	reg mult_start;
@@ -65,6 +67,8 @@ module Execute(
 			write_reg <= next_write_reg;
 			write_num <= next_write_num;
 			write_data <= next_write_data;
+			outpc <= pc;
+			outinsn <= insn;
 		end
 	end
 
diff --git a/system.v b/system.v
index 4601ae7..6fd0b8b 100644
--- a/system.v
+++ b/system.v
@@ -40,7 +40,6 @@ module System(input clk);
 	wire decode_out_carry;
 	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
 	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
-	wire execute_out_stall, execute_out_bubble;
 	wire execute_out_write_reg;
 	wire [3:0] execute_out_write_num;
 	wire [31:0] execute_out_write_data;
@@ -49,10 +48,13 @@ module System(input clk);
 	
 	wire bubble_out_fetch;
 	wire bubble_out_issue;
+	wire bubble_out_execute;
 	wire [31:0] insn_out_fetch;
 	wire [31:0] insn_out_issue;
+	wire [31:0] insn_out_execute;
 	wire [31:0] pc_out_fetch;
 	wire [31:0] pc_out_issue;
+	wire [31:0] pc_out_execute;
 
 	wire execute_out_backflush;
 
@@ -112,11 +114,11 @@ module System(input clk);
 		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
 		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
 		.op2(decode_out_op2), .carry(decode_out_carry),
-		.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
+		.outstall(stall_cause_execute), .outbubble(bubble_out_execute),
 		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
 		.write_data(execute_out_write_data),
-		.jmppc(jmppc),
-		.jmp(jmp));
+		.jmp(jmp), .jmppc(jmppc),
+		.outpc(pc_out_execute), .insn(insn_out_execute));
 	assign execute_out_backflush = jmp;
 
 	reg [31:0] clockno = 0;
@@ -127,6 +129,6 @@ module System(input clk);
 		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
 		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
 		$display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
-		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
+		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
 	end
 endmodule
-- 
2.39.2


From f5c8bf8ae6b59b66676c2f0bf6e2041fe56d61fc Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Mon, 5 Jan 2009 23:57:24 -0500
Subject: [PATCH 07/16] system.v: Silly typo fix -- why didn't Verilator warn
 me about that?????

---
 system.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/system.v b/system.v
index 6fd0b8b..a8a9ac4 100644
--- a/system.v
+++ b/system.v
@@ -118,7 +118,7 @@ module System(input clk);
 		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
 		.write_data(execute_out_write_data),
 		.jmp(jmp), .jmppc(jmppc),
-		.outpc(pc_out_execute), .insn(insn_out_execute));
+		.outpc(pc_out_execute), .outinsn(insn_out_execute));
 	assign execute_out_backflush = jmp;
 
 	reg [31:0] clockno = 0;
-- 
2.39.2


From 03f45381ee171bf7786182bc49c9de6a41436452 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 6 Jan 2009 00:53:29 -0500
Subject: [PATCH 08/16] System.v: Wire up DCache

---
 system.v | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/system.v b/system.v
index a8a9ac4..da9d701 100644
--- a/system.v
+++ b/system.v
@@ -1,4 +1,5 @@
 `define BUS_ICACHE 0
+`define BUS_DCACHE 1
 
 module System(input clk);
 	wire [7:0] bus_req;
@@ -9,23 +10,30 @@ module System(input clk);
 	wire bus_rd, bus_wr;
 	wire bus_ready;
 
-	wire bus_req_icache;	
-	assign bus_req = {7'b0, bus_req_icache};
+	wire bus_req_icache;
+	wire bus_req_dcache;
+	assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
 	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
+	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
 	
 	wire [31:0] bus_addr_icache;
 	wire [31:0] bus_wdata_icache;
 	wire bus_rd_icache;
 	wire bus_wr_icache;
 	
+	wire [31:0] bus_addr_dcache;
+	wire [31:0] bus_wdata_dcache;
+	wire bus_rd_dcache;
+	wire bus_wr_dcache;
+	
 	wire [31:0] bus_rdata_blockram;
 	wire bus_ready_blockram;
 	
-	assign bus_addr = bus_addr_icache;
+	assign bus_addr = bus_addr_icache | bus_addr_dcache;
 	assign bus_rdata = bus_rdata_blockram;
-	assign bus_wdata = bus_wdata_icache;
-	assign bus_rd = bus_rd_icache;
-	assign bus_wr = bus_wr_icache;
+	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
+	assign bus_rd = bus_rd_icache | bus_rd_dcache;
+	assign bus_wr = bus_wr_icache | bus_wr_dcache;
 	assign bus_ready = bus_ready_blockram;
 
 	wire [31:0] icache_rd_addr;
@@ -33,6 +41,11 @@ module System(input clk);
 	wire icache_rd_wait;
 	wire [31:0] icache_rd_data;
 	
+	wire [31:0] dcache_addr;
+	wire dcache_rd_req, dcache_wr_req;
+	wire dcache_rw_wait;
+	wire [31:0] dcache_wr_data, dcache_rd_data;
+	
 	wire stall_cause_issue;
 	wire stall_cause_execute;
 	
@@ -70,6 +83,15 @@ module System(input clk);
 		.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
 		.bus_wr(bus_wr_icache), .bus_ready(bus_ready));
 	
+	DCache dcache(
+		.clk(clk),
+		.addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
+		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
+		.bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
+		.bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
+		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
+		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
+
 	BlockRAM blockram(
 		.clk(clk),
 		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
-- 
2.39.2


From b3bb2fb8d24456b2683c5bdb8b3b195d0f600a97 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Tue, 6 Jan 2009 01:06:00 -0500
Subject: [PATCH 09/16] memory: preliminary, regfile: more read port, decode:
 more correct

---
 Decode.v  |   4 +-
 Memory.v  | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 RegFile.v |   7 +++
 3 files changed, 134 insertions(+), 2 deletions(-)
 create mode 100644 Memory.v

diff --git a/Decode.v b/Decode.v
index 359bbc0..a34eb3b 100644
--- a/Decode.v
+++ b/Decode.v
@@ -65,9 +65,9 @@ module Decode(
 		`DECODE_CDP,			/* Coprocessor data op */
 		`DECODE_MRCMCR,			/* Coprocessor register transfer */
 		`DECODE_SWI:			/* SWI */
-			rpc = inpc - 8;
+			rpc = inpc + 8;
 		`DECODE_ALU:			/* ALU */
-			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+			rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
 		default:			/* X everything else out */
 			rpc = 32'hxxxxxxxx;
 		endcase
diff --git a/Memory.v b/Memory.v
new file mode 100644
index 0000000..2b4b2a4
--- /dev/null
+++ b/Memory.v
@@ -0,0 +1,125 @@
+`include "ARM_Constants.v"
+
+module Memory(
+	input clk,
+	input Nrst,
+	input [31:0] pc,
+	input [31:0] insn,
+	input [31:0] base,
+	input [31:0] offset,
+
+	/* bus interface */
+	output reg [31:0] busaddr,
+	output reg rd_req,
+	output reg wr_req,
+	input rw_wait,
+	output reg [31:0] wr_data,
+	input [31:0] rd_data,
+
+	/* regfile interface */
+	output reg [3:0] st_read,
+	input [31:0] st_data,
+
+	/* writeback to base */
+	output reg writeback,
+	output reg [3:0] regsel,
+	output reg [31:0] regdata,
+
+	/* pc stuff */
+	output reg [31:0] outpc,
+	output reg [31:0] newpc,
+
+	/* stall */
+	output outstall,
+	output reg outbubble,
+	output reg flush
+);
+
+	reg [31:0] addr, raddr;
+	reg notdone = 1'b0;
+	reg inc_next = 1'b0;
+	wire [31:0] align_s1, align_s2, align_rddata;
+	assign outstall = rw_wait | notdone;
+
+	always @(*)
+	begin
+		addr = 32'hxxxxxxxx;
+		raddr = 32'hxxxxxxxx;
+		rd_req = 1'b0;
+		wr_req = 1'b0;
+		wr_data = 32'hxxxxxxxx;
+		busaddr = 32'hxxxxxxxx;
+		outstall = 1'b0;
+		casez(insn)
+		`DECODE_LDRSTR_UNDEFINED: begin end
+		`DECODE_LDRSTR: begin
+			addr = insn[23] ? base + offset : base - offset; /* up/down select */
+			raddr = insn[24] ? base : addr;
+			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+			rd_req = insn[20];
+			wr_req = ~insn[20];
+			if(!insn[20]) begin /* store */
+				st_read = insn[15:12];
+				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
+			end
+			else if(insn[15:12] == 4'hF)
+				flush = 1'b1;
+		end
+		`DECODE_LDMSTM: begin
+		end
+		default: begin end
+		endcase
+	end
+
+	assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+	assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+	assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+
+	always @(posedge clk)
+	begin
+		outpc <= pc;
+		outbubble <= rw_wait;
+		casez(insn)
+		`DECODE_LDRSTR_UNDEFINED: begin
+			writeback <= 1'b0;
+			regsel <= 4'hx;
+			regdata <= 32'hxxxxxxxx;
+			notdone <= 1'b0;
+		end
+		`DECODE_LDRSTR: begin
+			if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
+				if(insn[15:12] == 4'hF) begin
+					newpc <= align_rddata;
+				end
+				else begin
+					writeback <= 1'b1;
+					regsel <= insn[15:12];
+					regdata <= align_rddata;
+				end
+				inc_next <= 1'b1;
+			end
+			else if(insn[21]) begin /* write back */
+				writeback <= 1'b1;
+				regsel <= insn[19:16];
+				regdata <= addr;
+				inc_next <= 1'b0;
+			end else begin
+				writeback <= 1'b0;
+				inc_next <= 1'b0;
+				regsel <= 4'hx;
+				regdata <= 32'hxxxxxxxx;
+			end
+			notdone <= rw_wait & insn[20] & insn[21];
+		end
+		`DECODE_LDMSTM: begin
+		end
+		default: begin
+			writeback <= 1'b0;
+			regsel <= 4'hx;
+			regdata <= 32'hxxxxxxxx;
+			notdone <= 1'b0;
+		end
+		endcase
+	end
+
+endmodule
diff --git a/RegFile.v b/RegFile.v
index 95e5c71..1e94174 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,6 +6,8 @@ module RegFile(
 	output reg [31:0] rdata_1,
 	input [3:0] read_2,
 	output reg [31:0] rdata_2,
+	input [3:0] read_3,
+	output reg [31:0] rdata_3,
 	output reg [31:0] spsr,
 	input [3:0] write,
 	input write_req,
@@ -49,6 +51,11 @@ module RegFile(
 			rdata_2 = write_data;
 		else
 			rdata_2 = regfile[read_2];
+
+		if ((read_3 == write) && write_req)
+			rdata_3 = write_data;
+		else
+			rdata_3 = regfile[read_3];
 		
 		spsr = regfile[4'hF];
 	end
-- 
2.39.2


From 74d3729c44271277d935b105d5b1028510a23192 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Tue, 6 Jan 2009 01:34:42 -0500
Subject: [PATCH 10/16] memory: fixed up a bit

---
 Memory.v | 86 +++++++++++++++++++++++---------------------------------
 1 file changed, 35 insertions(+), 51 deletions(-)

diff --git a/Memory.v b/Memory.v
index 2b4b2a4..c4cee4d 100644
--- a/Memory.v
+++ b/Memory.v
@@ -31,14 +31,16 @@ module Memory(
 
 	/* stall */
 	output outstall,
-	output reg outbubble,
-	output reg flush
+	output reg outbubble
 );
 
-	reg [31:0] addr, raddr;
+	reg [31:0] addr, raddr, next_regdata, next_newpc;
+	reg [3:0] next_regsel;
+	reg next_writeback, next_notdone, next_inc_next;
+	reg [31:0] align_s1, align_s2, align_rddata;
+
 	reg notdone = 1'b0;
 	reg inc_next = 1'b0;
-	wire [31:0] align_s1, align_s2, align_rddata;
 	assign outstall = rw_wait | notdone;
 
 	always @(*)
@@ -50,6 +52,11 @@ module Memory(
 		wr_data = 32'hxxxxxxxx;
 		busaddr = 32'hxxxxxxxx;
 		outstall = 1'b0;
+		next_notdone = 1'b0;
+		next_regsel = 4'hx;
+		next_regdata = 32'hxxxxxxxx;
+		next_inc_next = 1'b0;
+		next_newpc = 32'hxxxxxxxx;
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
@@ -58,12 +65,27 @@ module Memory(
 			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
 			rd_req = insn[20];
 			wr_req = ~insn[20];
-			if(!insn[20]) begin /* store */
+
+			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+
+			if(!insn[20]) begin
 				st_read = insn[15:12];
 				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
 			end
-			else if(insn[15:12] == 4'hF)
-				flush = 1'b1;
+			else if(!inc_next) begin /* store */
+				next_writeback = 1'b1;
+				next_regsel = insn[15:12];
+				next_regdata = align_rddata;
+				next_inc_next = 1'b1;
+			end
+			else if(insn[21]) begin
+				next_writeback = 1'b1;
+				next_regsel = insn[19:16];
+				next_regdata = addr;
+			end
+			next_notdone = rw_wait & insn[20] & insn[21];
 		end
 		`DECODE_LDMSTM: begin
 		end
@@ -71,55 +93,17 @@ module Memory(
 		endcase
 	end
 
-	assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-	assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-	assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 
 	always @(posedge clk)
 	begin
 		outpc <= pc;
 		outbubble <= rw_wait;
-		casez(insn)
-		`DECODE_LDRSTR_UNDEFINED: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
-		`DECODE_LDRSTR: begin
-			if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
-				if(insn[15:12] == 4'hF) begin
-					newpc <= align_rddata;
-				end
-				else begin
-					writeback <= 1'b1;
-					regsel <= insn[15:12];
-					regdata <= align_rddata;
-				end
-				inc_next <= 1'b1;
-			end
-			else if(insn[21]) begin /* write back */
-				writeback <= 1'b1;
-				regsel <= insn[19:16];
-				regdata <= addr;
-				inc_next <= 1'b0;
-			end else begin
-				writeback <= 1'b0;
-				inc_next <= 1'b0;
-				regsel <= 4'hx;
-				regdata <= 32'hxxxxxxxx;
-			end
-			notdone <= rw_wait & insn[20] & insn[21];
-		end
-		`DECODE_LDMSTM: begin
-		end
-		default: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
-		endcase
+		writeback <= next_writeback;
+		regsel <= next_regsel;
+		regdata <= next_regdata;
+		notdone <= next_notdone;
+		newpc <= next_newpc;
+		inc_next <= next_inc_next;
 	end
 
 endmodule
-- 
2.39.2


From 5bcb3b7e4f103f6d4992992c396a8f6e2c42a637 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Tue, 6 Jan 2009 01:39:32 -0500
Subject: [PATCH 11/16] memory: fix up slightly

---
 Memory.v | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/Memory.v b/Memory.v
index c4cee4d..409b282 100644
--- a/Memory.v
+++ b/Memory.v
@@ -27,14 +27,13 @@ module Memory(
 
 	/* pc stuff */
 	output reg [31:0] outpc,
-	output reg [31:0] newpc,
 
 	/* stall */
 	output outstall,
 	output reg outbubble
 );
 
-	reg [31:0] addr, raddr, next_regdata, next_newpc;
+	reg [31:0] addr, raddr, next_regdata;
 	reg [3:0] next_regsel;
 	reg next_writeback, next_notdone, next_inc_next;
 	reg [31:0] align_s1, align_s2, align_rddata;
@@ -56,7 +55,6 @@ module Memory(
 		next_regsel = 4'hx;
 		next_regdata = 32'hxxxxxxxx;
 		next_inc_next = 1'b0;
-		next_newpc = 32'hxxxxxxxx;
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
@@ -66,15 +64,17 @@ module Memory(
 			rd_req = insn[20];
 			wr_req = ~insn[20];
 
+			/* rotate to correct position */
 			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+			/* select byte or word */
 			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 
 			if(!insn[20]) begin
 				st_read = insn[15:12];
-				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
+				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
 			end
-			else if(!inc_next) begin /* store */
+			else if(!inc_next) begin
 				next_writeback = 1'b1;
 				next_regsel = insn[15:12];
 				next_regdata = align_rddata;
@@ -102,7 +102,6 @@ module Memory(
 		regsel <= next_regsel;
 		regdata <= next_regdata;
 		notdone <= next_notdone;
-		newpc <= next_newpc;
 		inc_next <= next_inc_next;
 	end
 
-- 
2.39.2


From a02ca509af0305e3c94127433b47efe39c25c88f Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 6 Jan 2009 02:24:32 -0500
Subject: [PATCH 12/16] Memory.v: Cleanup pass 1 before integration.

---
 Memory.v | 128 ++++++++++++++++++++++++++++++-------------------------
 1 file changed, 70 insertions(+), 58 deletions(-)

diff --git a/Memory.v b/Memory.v
index 409b282..9c010e7 100644
--- a/Memory.v
+++ b/Memory.v
@@ -3,10 +3,6 @@
 module Memory(
 	input clk,
 	input Nrst,
-	input [31:0] pc,
-	input [31:0] insn,
-	input [31:0] base,
-	input [31:0] offset,
 
 	/* bus interface */
 	output reg [31:0] busaddr,
@@ -19,28 +15,50 @@ module Memory(
 	/* regfile interface */
 	output reg [3:0] st_read,
 	input [31:0] st_data,
+	
+	/* stage inputs */
+	input inbubble,
+	input [31:0] pc,
+	input [31:0] insn,
+	input [31:0] base,
+	input [31:0] offset,
+	input write_reg,
+	input [3:0] write_num,
+	input [31:0] write_data,
 
-	/* writeback to base */
-	output reg writeback,
-	output reg [3:0] regsel,
-	output reg [31:0] regdata,
-
-	/* pc stuff */
+	/* outputs */
+	output reg outstall,
+	output reg outbubble,
 	output reg [31:0] outpc,
-
-	/* stall */
-	output outstall,
-	output reg outbubble
-);
+	output reg [31:0] outinsn,
+	output reg out_write_reg = 1'b0,
+	output reg [3:0] out_write_num = 4'bxxxx,
+	output reg [31:0] out_write_data = 32'hxxxxxxxx
+	);
 
 	reg [31:0] addr, raddr, next_regdata;
 	reg [3:0] next_regsel;
 	reg next_writeback, next_notdone, next_inc_next;
 	reg [31:0] align_s1, align_s2, align_rddata;
+	
+	wire next_write_reg;
+	wire [3:0] next_write_num;
+	wire [31:0] next_write_data;
 
 	reg notdone = 1'b0;
 	reg inc_next = 1'b0;
-	assign outstall = rw_wait | notdone;
+
+	always @(posedge clk)
+	begin
+		outpc <= pc;
+		outinsn <= insn;
+		outbubble <= rw_wait;
+		out_write_reg <= next_writeback;
+		out_write_num <= next_regsel;
+		out_write_data <= next_regdata;
+		notdone <= next_notdone;
+		inc_next <= next_inc_next;
+	end
 
 	always @(*)
 	begin
@@ -52,57 +70,51 @@ module Memory(
 		busaddr = 32'hxxxxxxxx;
 		outstall = 1'b0;
 		next_notdone = 1'b0;
-		next_regsel = 4'hx;
-		next_regdata = 32'hxxxxxxxx;
+		next_write_reg = write_reg;
+		next_write_num = write_num;
+		next_write_data = write_data;
 		next_inc_next = 1'b0;
+		outstall = 1'b0;
+		
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
-			addr = insn[23] ? base + offset : base - offset; /* up/down select */
-			raddr = insn[24] ? base : addr;
-			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
-			rd_req = insn[20];
-			wr_req = ~insn[20];
-
-			/* rotate to correct position */
-			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-			/* select byte or word */
-			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
-			if(!insn[20]) begin
-				st_read = insn[15:12];
-				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+			if (!inbubble) begin
+				outstall = rw_wait | notdone;
+			
+				addr = insn[23] ? base + offset : base - offset; /* up/down select */
+				raddr = insn[24] ? base : addr;
+				busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+				rd_req = insn[20];
+				wr_req = ~insn[20];
+				
+				/* rotate to correct position */
+				align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+				align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+				/* select byte or word */
+				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+				
+				if(!insn[20]) begin
+					st_read = insn[15:12];
+					wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+				end
+				else if(!inc_next) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[15:12];
+					next_write_data = align_rddata;
+					next_inc_next = 1'b1;
+				end
+				else if(insn[21]) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[19:16];
+					next_write_data = addr;
+				end
+				next_notdone = rw_wait & insn[20] & insn[21];
 			end
-			else if(!inc_next) begin
-				next_writeback = 1'b1;
-				next_regsel = insn[15:12];
-				next_regdata = align_rddata;
-				next_inc_next = 1'b1;
-			end
-			else if(insn[21]) begin
-				next_writeback = 1'b1;
-				next_regsel = insn[19:16];
-				next_regdata = addr;
-			end
-			next_notdone = rw_wait & insn[20] & insn[21];
 		end
 		`DECODE_LDMSTM: begin
 		end
 		default: begin end
 		endcase
 	end
-
-
-	always @(posedge clk)
-	begin
-		outpc <= pc;
-		outbubble <= rw_wait;
-		writeback <= next_writeback;
-		regsel <= next_regsel;
-		regdata <= next_regdata;
-		notdone <= next_notdone;
-		inc_next <= next_inc_next;
-	end
-
 endmodule
-- 
2.39.2


From b783a475f7d452cdca00640b3333bbf72bfbd6b7 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Tue, 6 Jan 2009 02:27:04 -0500
Subject: [PATCH 13/16] memory: add some stuff in ldm/stm

---
 Memory.v | 51 +++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/Memory.v b/Memory.v
index 409b282..3eb39b3 100644
--- a/Memory.v
+++ b/Memory.v
@@ -5,8 +5,8 @@ module Memory(
 	input Nrst,
 	input [31:0] pc,
 	input [31:0] insn,
-	input [31:0] base,
-	input [31:0] offset,
+	input [31:0] op0,
+	input [31:0] op1,
 
 	/* bus interface */
 	output reg [31:0] busaddr,
@@ -37,6 +37,7 @@ module Memory(
 	reg [3:0] next_regsel;
 	reg next_writeback, next_notdone, next_inc_next;
 	reg [31:0] align_s1, align_s2, align_rddata;
+	reg [15:0] regs, next_regs;
 
 	reg notdone = 1'b0;
 	reg inc_next = 1'b0;
@@ -58,8 +59,8 @@ module Memory(
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
-			addr = insn[23] ? base + offset : base - offset; /* up/down select */
-			raddr = insn[24] ? base : addr;
+			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+			raddr = insn[24] ? op0 : addr;
 			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
 			rd_req = insn[20];
 			wr_req = ~insn[20];
@@ -88,6 +89,47 @@ module Memory(
 			next_notdone = rw_wait & insn[20] & insn[21];
 		end
 		`DECODE_LDMSTM: begin
+			busaddr = {op0[31:2], 2'b0};
+			rd_req = insn[20];
+			wr_req = ~insn[20];
+			casez(regs)
+			16'b???????????????1: begin
+				next_regs = regs;
+			end
+			16'b??????????????10: begin
+			end
+			16'b?????????????100: begin
+			end
+			16'b????????????1000: begin
+			end
+			16'b???????????10000: begin
+			end
+			16'b??????????100000: begin
+			end
+			16'b?????????1000000: begin
+			end
+			16'b????????10000000: begin
+			end
+			16'b???????100000000: begin
+			end
+			16'b??????1000000000: begin
+			end
+			16'b?????10000000000: begin
+			end
+			16'b????100000000000: begin
+			end
+			16'b???1000000000000: begin
+			end
+			16'b??10000000000000: begin
+			end
+			16'b?100000000000000: begin
+			end
+			16'b1000000000000000: begin
+			end
+			default: begin
+				next_inc_next = 1'b1;
+			end
+			endcase
 		end
 		default: begin end
 		endcase
@@ -103,6 +145,7 @@ module Memory(
 		regdata <= next_regdata;
 		notdone <= next_notdone;
 		inc_next <= next_inc_next;
+		regs <= next_regs;
 	end
 
 endmodule
-- 
2.39.2


From 6d0f9d8259aa4b3624bfec65b679ee42e54f7875 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 6 Jan 2009 02:50:55 -0500
Subject: [PATCH 14/16] st_data -> op2

---
 Decode.v | 2 ++
 Memory.v | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Decode.v b/Decode.v
index a34eb3b..b58951a 100644
--- a/Decode.v
+++ b/Decode.v
@@ -171,6 +171,7 @@ module Decode(
 		begin
 			read_0 = insn[19:16]; /* Rn */
 			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[15:12];
 			
 			op0_out = regs0;
 			if(insn[25]) begin
@@ -180,6 +181,7 @@ module Decode(
 				op1_out = shift_res;
 				carry_out = shift_cflag_out;
 			end
+			op2_out = regs2;
 		end
 		`DECODE_LDMSTM:		/* Block data transfer */
 		begin
diff --git a/Memory.v b/Memory.v
index 4af216d..2378177 100644
--- a/Memory.v
+++ b/Memory.v
@@ -22,6 +22,7 @@ module Memory(
 	input [31:0] insn,
 	input [31:0] op0,
 	input [31:0] op1,
+	input [31:0] op2,
 	input write_reg,
 	input [3:0] write_num,
 	input [31:0] write_data,
@@ -98,8 +99,7 @@ module Memory(
 				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 				
 				if(!insn[20]) begin
-					st_read = insn[15:12];
-					wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+					wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
 				end
 				else if(!inc_next) begin
 					next_write_reg = 1'b1;
-- 
2.39.2


From c65110a8c83463c0f95391c2ec7e0277de333c62 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 6 Jan 2009 03:15:58 -0500
Subject: [PATCH 15/16] Wire in Memory.  Fix small bug in Memory involving
 registers never ever getting output (type A...).

---
 Execute.v |  6 +++++-
 Memory.v  | 18 ++++++++++--------
 system.v  | 42 +++++++++++++++++++++++++++++++++---------
 3 files changed, 48 insertions(+), 18 deletions(-)

diff --git a/Execute.v b/Execute.v
index cd71d76..7f4cf6c 100644
--- a/Execute.v
+++ b/Execute.v
@@ -25,7 +25,8 @@ module Execute(
 	output reg [31:0] jmppc,
 	output reg jmp,
 	output reg [31:0] outpc,
-	output reg [31:0] outinsn
+	output reg [31:0] outinsn,
+	output reg [31:0] outop0, outop1, outop2
 	);
 	
 	reg mult_start;
@@ -69,6 +70,9 @@ module Execute(
 			write_data <= next_write_data;
 			outpc <= pc;
 			outinsn <= insn;
+			outop0 <= op0;
+			outop1 <= op1;
+			outop2 <= op2;
 		end
 	end
 
diff --git a/Memory.v b/Memory.v
index 2378177..e10a2e7 100644
--- a/Memory.v
+++ b/Memory.v
@@ -37,11 +37,11 @@ module Memory(
 	output reg [31:0] out_write_data = 32'hxxxxxxxx
 	);
 
-	reg [31:0] addr, raddr, next_regdata;
-	reg [3:0] next_regsel;
-	reg next_writeback, next_notdone, next_inc_next;
+	reg [31:0] addr, raddr;
+	reg next_notdone, next_inc_next;
 	reg [31:0] align_s1, align_s2, align_rddata;
-	
+
+	wire next_outbubble;	
 	wire next_write_reg;
 	wire [3:0] next_write_num;
 	wire [31:0] next_write_data;
@@ -55,10 +55,10 @@ module Memory(
 	begin
 		outpc <= pc;
 		outinsn <= insn;
-		outbubble <= rw_wait;
-		out_write_reg <= next_writeback;
-		out_write_num <= next_regsel;
-		out_write_data <= next_regdata;
+		outbubble <= next_outbubble;
+		out_write_reg <= next_write_reg;
+		out_write_num <= next_write_num;
+		out_write_data <= next_write_data;
 		notdone <= next_notdone;
 		inc_next <= next_inc_next;
 		regs <= next_regs;
@@ -78,12 +78,14 @@ module Memory(
 		next_write_num = write_num;
 		next_write_data = write_data;
 		next_inc_next = 1'b0;
+		next_outbubble = inbubble;
 		outstall = 1'b0;
 		
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
 			if (!inbubble) begin
+				next_outbubble = rw_wait;
 				outstall = rw_wait | notdone;
 			
 				addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
diff --git a/system.v b/system.v
index da9d701..a0c35d6 100644
--- a/system.v
+++ b/system.v
@@ -46,28 +46,38 @@ module System(input clk);
 	wire dcache_rw_wait;
 	wire [31:0] dcache_wr_data, dcache_rd_data;
 	
-	wire stall_cause_issue;
-	wire stall_cause_execute;
-	
 	wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
 	wire decode_out_carry;
-	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
-	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
+	
+	wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
+	wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
+	
 	wire execute_out_write_reg;
 	wire [3:0] execute_out_write_num;
 	wire [31:0] execute_out_write_data;
+	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
 	wire [31:0] jmppc;
 	wire jmp;
 	
+	wire memory_out_write_reg;
+	wire [3:0] memory_out_write_num;
+	wire [31:0] memory_out_write_data;
+	
+	wire stall_cause_issue;
+	wire stall_cause_execute;
+	wire stall_cause_memory;
 	wire bubble_out_fetch;
 	wire bubble_out_issue;
 	wire bubble_out_execute;
+	wire bubble_out_memory;
 	wire [31:0] insn_out_fetch;
 	wire [31:0] insn_out_issue;
 	wire [31:0] insn_out_execute;
+	wire [31:0] insn_out_memory;
 	wire [31:0] pc_out_fetch;
 	wire [31:0] pc_out_issue;
 	wire [31:0] pc_out_execute;
+	wire [31:0] pc_out_memory;
 
 	wire execute_out_backflush;
 
@@ -118,8 +128,8 @@ module System(input clk);
 	
 	RegFile regfile(
 		.clk(clk),
-		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
-		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
+		.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3),
+		.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3),
 		.spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
 	
 	Decode decode(
@@ -132,7 +142,7 @@ module System(input clk);
 	
 	Execute execute(
 		.clk(clk), .Nrst(1'b0),
-		.stall(1'b0 /* XXX */), .flush(1'b0),
+		.stall(stall_cause_memory), .flush(1'b0),
 		.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
 		.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
 		.op2(decode_out_op2), .carry(decode_out_carry),
@@ -140,8 +150,21 @@ module System(input clk);
 		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
 		.write_data(execute_out_write_data),
 		.jmp(jmp), .jmppc(jmppc),
-		.outpc(pc_out_execute), .outinsn(insn_out_execute));
+		.outpc(pc_out_execute), .outinsn(insn_out_execute),
+		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2));
 	assign execute_out_backflush = jmp;
+	
+	Memory memory(
+		.clk(clk), .Nrst(1'b0),
+		/* stall? flush? */
+		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
+		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
+		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
+		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
+		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
+		.outpc(pc_out_memory), .outinsn(insn_out_memory),
+		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
+		.out_write_data(memory_out_write_data));
 
 	reg [31:0] clockno = 0;
 	always @(posedge clk)
@@ -152,5 +175,6 @@ module System(input clk);
 		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
 		$display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
 		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc);
+		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
 	end
 endmodule
-- 
2.39.2


From b455d4811bb209ccddf70e8789a9efcb92536121 Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Tue, 6 Jan 2009 03:17:27 -0500
Subject: [PATCH 16/16] system: Remember to wire the DCache to the memory!

---
 system.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/system.v b/system.v
index a0c35d6..fdefc54 100644
--- a/system.v
+++ b/system.v
@@ -157,6 +157,8 @@ module System(input clk);
 	Memory memory(
 		.clk(clk), .Nrst(1'b0),
 		/* stall? flush? */
+		.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
+		.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
 		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
 		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
 		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
-- 
2.39.2