From 8744c23dbf6a3c38649c800ae3d96e7e465e01fb Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Wed, 18 Mar 2009 11:46:43 -0400 Subject: [PATCH] xst: Add synthesis files (part 1). --- xst/Console.v | 436 ++++++++ xst/FireARM.ucf | 33 + xst/FireARM.xst | 57 + xst/Makefile | 88 ++ xst/ibmpc1.mem | 2050 +++++++++++++++++++++++++++++++++++ xst/iic_init.v | 219 ++++ xst/impact.cmd | 7 + xst/ram.hex | 1 + xst/scancodes.shifted.hex | 128 +++ xst/scancodes.unshifted.hex | 128 +++ xst/sim/tb.v | 15 + 11 files changed, 3162 insertions(+) create mode 100644 xst/Console.v create mode 100644 xst/FireARM.ucf create mode 100644 xst/FireARM.xst create mode 100644 xst/Makefile create mode 100644 xst/ibmpc1.mem create mode 100644 xst/iic_init.v create mode 100644 xst/impact.cmd create mode 120000 xst/ram.hex create mode 100644 xst/scancodes.shifted.hex create mode 100644 xst/scancodes.unshifted.hex create mode 100644 xst/sim/tb.v diff --git a/xst/Console.v b/xst/Console.v new file mode 100644 index 0000000..5f5e2da --- /dev/null +++ b/xst/Console.v @@ -0,0 +1,436 @@ +module MulDivDCM(input xtal, output clk, output clk90); + parameter div = 8; + parameter mul = 2; + + wire CLKFX_BUF; + wire CLK0_BUF; + wire CLK90_BUF; + wire clkfx; + wire GND_BIT = 0; + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(clk)); + BUFG CLK90_BUFG_INST (.I(CLK90_BUF), + .O(clk90)); + BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), + .O(clkfx)); + + DCM_BASE DCM_INST2(.CLKFB(clk), + .CLKIN(clkfx), + .RST(GND_BIT), + .CLK0(CLK0_BUF), + .CLK90(CLK90_BUF)); + + DCM_BASE DCM_INST (.CLKFB(GND_BIT), + .CLKIN(xtal), + .RST(GND_BIT), + .CLKFX(CLKFX_BUF)); + defparam DCM_INST.CLK_FEEDBACK = "NONE"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = div; + defparam DCM_INST.CLKFX_MULTIPLY = mul; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'hC080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "TRUE"; +endmodule + +`include "iic_init.v" + +module Console( + input xtal, + input rst, + output wire rstact, + output wire dvi_vs, dvi_hs, + output wire [11:0] dvi_d, + output wire dvi_xclk_p, dvi_xclk_n, + output wire dvi_de, + output wire dvi_reset_b, + inout wire dvi_sda, + inout wire dvi_scl, + input ps2c, ps2d); + + assign dvi_reset_b = 1'b1; + + wire clk25, clk25_90; + + wire [11:0] x, y; + wire border; + + MulDivDCM dcm25(xtal, clk25, clk25_90); + defparam dcm25.div = 16; + defparam dcm25.mul = 5; + + wire vs, hs; + SyncGen sync(clk25, vs, hs, x, y, border); + + wire [7:0] cschar; + wire [2:0] csrow; + wire [7:0] csdata; + + wire [10:0] vraddr; + wire [7:0] vrdata; + + wire [10:0] vwaddr; + wire [7:0] vwdata; + wire [7:0] serdata; + wire vwr, serwr; + wire [10:0] vscroll; + + wire odata; + + wire [6:0] vcursx; + wire [4:0] vcursy; + + reg [16:0] rsttimer = 17'h3FFFF; + always @(posedge clk25) + if (~rst) + rsttimer <= 17'h3FFFF; + else if (rsttimer) + rsttimer <= rsttimer - 1; + assign rstact = rsttimer != 17'h0; + + wire tookdata; + reg ps2_hasd = 0; + reg [7:0] ps2_d = 0; + wire sertxwr; + wire [7:0] sertxdata; + + CharSet cs(cschar, csrow, csdata); + VideoRAM vram(clk25, vraddr + vscroll, vrdata, clk25, vwaddr, vwdata, vwr); + VDisplay dpy(clk25, x, y, vraddr, vrdata, cschar, csrow, csdata, vcursx, vcursy, odata); + RXState rxsm(clk25, vwr, vwaddr, vwdata, vscroll, vcursx, vcursy, serwr, serdata); + PS2 ps2(clk25, ps2c, ps2d, sertxwr, sertxdata); + System sys(.clk(clk25), .rst(rstact), .sys_odata({serwr, serdata}), .sys_idata({ps2_hasd, ps2_d}), .sys_tookdata(tookdata)); + + always @(posedge clk25) + if (sertxwr) + {ps2_hasd, ps2_d} <= {1'b1, sertxdata}; + else if (tookdata) + {ps2_hasd, ps2_d} <= {1'b0, 8'hxxxxxxxx}; + + /* FUCK! ASS! BALLS! EAT MY SHORT DICK! FUCKING XST */ + /* EMSD stands for Eat My Short Dick. Because XST should. */ +`define MAKE_DDR(n,q,d1,d2) ODDR n (.C(clk25), .Q(q), .D1(d1), .D2(d2), .R(0), .S(0), .CE(1)) +`define MAKE_DDR90(n,q,d1,d2) ODDR n (.C(clk25_90), .Q(q), .D1(d1), .D2(d2), .R(0), .S(0), .CE(1)) + + wire [7:0] red, green, blue; + assign red = (odata ? 8'hFF : 0) | (x[8:2] ^ y[7:1]); + assign green = (odata ? 8'hFF : 0) | (x[7:1] ^ y[8:2]); + assign blue = (odata ? 8'hFF : 0) | (x[8:2] ^ y[8:2]); + + `MAKE_DDR90(EMSD_dvi_xclk_p, dvi_xclk_p, 1'b1, 1'b0); + `MAKE_DDR90(EMSD_dvi_xclk_n, dvi_xclk_n, 1'b0, 1'b1); + `MAKE_DDR(EMSD_dvi_de, dvi_de, ~border, ~border); + `MAKE_DDR(EMSD_dvi_vs, dvi_vs, vs, vs); + `MAKE_DDR(EMSD_dvi_hs, dvi_hs, hs, hs); + `MAKE_DDR(EMSD_dvi_d_0, dvi_d[0], blue[0], green[4]); + `MAKE_DDR(EMSD_dvi_d_1, dvi_d[1], blue[1], green[5]); + `MAKE_DDR(EMSD_dvi_d_2, dvi_d[2], blue[2], green[6]); + `MAKE_DDR(EMSD_dvi_d_3, dvi_d[3], blue[3], green[7]); + `MAKE_DDR(EMSD_dvi_d_4, dvi_d[4], blue[4], red[0]); + `MAKE_DDR(EMSD_dvi_d_5, dvi_d[5], blue[5], red[1]); + `MAKE_DDR(EMSD_dvi_d_6, dvi_d[6], blue[6], red[2]); + `MAKE_DDR(EMSD_dvi_d_7, dvi_d[7], blue[7], red[3]); + `MAKE_DDR(EMSD_dvi_d_8, dvi_d[8], green[0], red[4]); + `MAKE_DDR(EMSD_dvi_d_9, dvi_d[9], green[1], red[5]); + `MAKE_DDR(EMSD_dvi_d_10, dvi_d[10], green[2], red[6]); + `MAKE_DDR(EMSD_dvi_d_11, dvi_d[11], green[3], red[7]); + + wire wee; + iic_init #(.CLK_RATE_MHZ(31)) init (clk25, 1'b1, 1'b0, dvi_sda, dvi_scl, wee); + +endmodule + +module SyncGen( + input pixclk, + output reg vs, hs, + output reg [11:0] x, y, + output reg border); + + parameter XRES = 640; + parameter XFPORCH = 24; + parameter XSYNC = 40; + parameter XBPORCH = 128; + + parameter YRES = 480; + parameter YFPORCH = 9; + parameter YSYNC = 3; + parameter YBPORCH = 28; + + always @(posedge pixclk) + begin + if (x >= (XRES + XFPORCH + XSYNC + XBPORCH)) + begin + if (y >= (YRES + YFPORCH + YSYNC + YBPORCH)) + y = 0; + else + y = y + 1; + x = 0; + end else + x = x + 1; + hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC)); + vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC)); + border <= (x > XRES) || (y > YRES); + end +endmodule + +module CharSet( + input [7:0] char, + input [2:0] row, + output wire [7:0] data); + + reg [7:0] rom [(256 * 8 - 1):0]; + + initial + $readmemb("ibmpc1.mem", rom); + + assign data = rom[{char, row}]; +endmodule + +module VideoRAM( + input pixclk, + input [10:0] raddr, + output reg [7:0] rdata, + input wclk, + input [10:0] waddr, + input [7:0] wdata, + input wr); + + reg [7:0] ram [2047 : 0]; + + always @(posedge pixclk) + rdata <= ram[raddr]; + + always @(posedge wclk) + if (wr) + ram[waddr] <= wdata; +endmodule + +module VDisplay( + input pixclk, + input [11:0] x, + input [11:0] y, + output wire [10:0] raddr, + input [7:0] rchar, + output wire [7:0] cschar, + output wire [2:0] csrow, + input [7:0] csdata, + input [6:0] cursx, + input [4:0] cursy, + output reg data); + + wire [7:0] col = x[11:3]; + wire [5:0] row = y[10:4]; + reg [7:0] ch; + reg [11:0] xdly; + + assign raddr = ({row,4'b0} + {row,6'b0} + {4'h0,col}); + assign cschar = rchar; + assign csrow = y[3:1]; + + reg [23:0] blinktime = 0; + + always @(posedge pixclk) blinktime <= blinktime + 1; + + wire curssel = (cursx == col) && (cursy == row) && blinktime[23]; + + always @(posedge pixclk) + xdly <= x; + + always @(posedge pixclk) + data = ((xdly < 80 * 8) && (y < 25 * 16)) ? (csdata[7 - xdly[2:0]] ^ curssel) : 0; +endmodule + +module RXState( + input clk25, + output reg vwr = 0, + output reg [10:0] vwaddr = 0, + output reg [7:0] vwdata = 0, + output reg [10:0] vscroll = 0, + output wire [6:0] vcursx, + output wire [4:0] vcursy, + input serwr, + input [7:0] serdata); + + parameter STATE_IDLE = 4'b0000; + parameter STATE_NEWLINE = 4'b0001; + parameter STATE_CLEAR = 4'b0010; + + reg [3:0] state = STATE_CLEAR; + + reg [6:0] x = 0; + reg [4:0] y = 0; + + assign vcursx = x; + assign vcursy = y; + + reg [10:0] clearstart = 0; + reg [10:0] clearend = 11'b11111111111; + + always @(posedge clk25) + case (state) + STATE_IDLE: if (serwr) begin + if (serdata == 8'h0A) begin + state <= STATE_NEWLINE; + x <= 0; + vwr <= 0; + end else if (serdata == 8'h0D) begin + x <= 0; + vwr <= 0; + end else if (serdata == 8'h0C) begin + clearstart <= 0; + clearend <= 11'b11111111111; + x <= 0; + y <= 0; + vscroll <= 0; + state <= STATE_CLEAR; + end else if (serdata == 8'h08) begin + if (x != 0) + x <= x - 1; + vwr <= 0; + end else begin + vwr <= 1; + vwaddr <= ({y,4'b0} + {y,6'b0} + {4'h0,x}) + vscroll; + vwdata <= serdata; + if (x == 79) begin + x <= 0; + state <= STATE_NEWLINE; + end else + x <= x + 1; + end + end + STATE_NEWLINE: + begin + vwr <= 0; + if (y == 24) begin + vscroll <= vscroll + 80; + clearstart <= (25 * 80) + vscroll; + clearend <= (26*80) + vscroll; + state <= STATE_CLEAR; + end else begin + y <= y + 1; + state <= STATE_IDLE; + end + end + STATE_CLEAR: + begin + vwr <= 1; + vwaddr <= clearstart; + vwdata <= 8'h20; + clearstart <= clearstart + 1; + if (clearstart == clearend) + state <= STATE_IDLE; + end + endcase +endmodule + +module PS2( + input pixclk, + input inclk, + input indata, + output reg wr, + output reg [7:0] data + ); + + reg [3:0] bitcount = 0; + reg [7:0] key = 0; + reg keyarrow = 0, keyup = 0, parity = 0; + + + /* Clock debouncing */ + reg lastinclk = 0; + reg [6:0] debounce = 0; + reg fixedclk = 0; + reg [11:0] resetcountdown = 0; + + reg [6:0] unshiftedrom [127:0]; initial $readmemh("scancodes.unshifted.hex", unshiftedrom); + reg [6:0] shiftedrom [127:0]; initial $readmemh("scancodes.shifted.hex", shiftedrom); + + reg mod_lshift = 0; + reg mod_rshift = 0; + reg mod_capslock = 0; + wire mod_shifted = (mod_lshift | mod_rshift) ^ mod_capslock; + + reg nd = 0; + reg lastnd = 0; + + always @(posedge pixclk) begin + if (inclk != lastinclk) begin + lastinclk <= inclk; + debounce <= 1; + resetcountdown <= 12'b111111111111; + end else if (debounce == 0) begin + fixedclk <= inclk; + resetcountdown <= resetcountdown - 1; + end else + debounce <= debounce + 1; + + if (nd ^ lastnd) begin + lastnd <= nd; + wr <= 1; + end else + wr <= 0; + end + + always @(negedge fixedclk) begin + if (resetcountdown == 0) + bitcount <= 0; + else if (bitcount == 10) begin + bitcount <= 0; + if(parity != (^ key)) begin + if(keyarrow) begin + casex(key) + 8'hF0: keyup <= 1; + 8'hxx: keyarrow <= 0; + endcase + end + else begin + if(keyup) begin + keyup <= 0; + keyarrow <= 0; + casex (key) + 8'h12: mod_lshift <= 0; + 8'h59: mod_rshift <= 0; + endcase + // handle this? I don't fucking know + end + else begin + casex(key) + 8'hE0: keyarrow <= 1; // handle these? I don't fucking know + 8'hF0: keyup <= 1; + 8'h12: mod_lshift <= 1; + 8'h59: mod_rshift <= 1; + 8'h14: mod_capslock <= ~mod_capslock; + 8'b0xxxxxxx: begin nd <= ~nd; data <= mod_shifted ? shiftedrom[key] : unshiftedrom[key]; end + 8'b1xxxxxxx: begin /* AAAAAAASSSSSSSS */ end + endcase + end + end + end + else begin + keyarrow <= 0; + keyup <= 0; + end + end else + bitcount <= bitcount + 1; + + case(bitcount) + 1: key[0] <= indata; + 2: key[1] <= indata; + 3: key[2] <= indata; + 4: key[3] <= indata; + 5: key[4] <= indata; + 6: key[5] <= indata; + 7: key[6] <= indata; + 8: key[7] <= indata; + 9: parity <= indata; + endcase + end + +endmodule diff --git a/xst/FireARM.ucf b/xst/FireARM.ucf new file mode 100644 index 0000000..d26adb9 --- /dev/null +++ b/xst/FireARM.ucf @@ -0,0 +1,33 @@ +NET "xtal" LOC="ah15" | CLOCK_DEDICATED_ROUTE = FALSE | TNM_NET = xtal; +TIMESPEC "TS_xtal"=PERIOD "xtal" 100 MHz HIGH 50%; + +NET "dvi_d<11>" LOC="AN14" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<10>" LOC="AP14" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<9>" LOC="AB10" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<8>" LOC="AA10" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<7>" LOC="AN13" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<6>" LOC="AM13" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<5>" LOC="AA8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<4>" LOC="AA9" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<3>" LOC="AP12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<2>" LOC="AN12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<1>" LOC="AC8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_d<0>" LOC="AB8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_xclk_p" LOC="AL11" | TNM="dvi_c" | IOSTANDARD=LVDCI_33; +NET "dvi_xclk_n" LOC="AL10" | TNM="dvi_c" | IOSTANDARD=LVDCI_33; +NET "dvi_hs" LOC="AM12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_vs" LOC="AM11" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_de" LOC="AE8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; +NET "dvi_reset_b" LOC="AK6" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; + +NET "dvi_scl" LOC="u27" | SLEW=fast | PULLUP; +NET "dvi_sda" LOC="t29" | SLEW=fast | PULLUP; + +TIMESPEC "TS_dvi_setup" = FROM dvi_c TO dvi_d 500 ps; +TIMESPEC "TS_dvi_hold" = FROM dvi_d TO dvi_c 500 ps; + +NET "rst" LOC="E9"; +NET "rstact" LOC="F6"; + +NET "ps2c" LOC="T26" | CLOCK_DEDICATED_ROUTE = FALSE; +NET "ps2d" LOC="T25"; diff --git a/xst/FireARM.xst b/xst/FireARM.xst new file mode 100644 index 0000000..01b1093 --- /dev/null +++ b/xst/FireARM.xst @@ -0,0 +1,57 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn FireARM.prj +-ifmt mixed +-ofn FireARM +-ofmt NGC +-p xc5vlx110t-1-ff1136 +-top Console +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso FireARM.lso +-keep_hierarchy NO +-netlist_hierarchy as_optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xst/Makefile b/xst/Makefile new file mode 100644 index 0000000..074ec26 --- /dev/null +++ b/xst/Makefile @@ -0,0 +1,88 @@ +TARGET = FireARM +VLOGS = Console.v ARM_Constants.v BigBlockRAM.v BlockRAM.v BusArbiter.v DCache.v Decode.v Execute.v Fetch.v ICache.v Issue.v Memory.v RegFile.v system.v Terminal.v Writeback.v +VLOGS_ALL = $(VLOGS) ram.hex + +all: fpga_target + +BITGEN_OPTS = \ + -w \ + -g DebugBitstream:No \ + -g Binary:no \ + -g CRC:Enable \ + -g ProgPin:PullUp \ + -g DonePin:PullUp \ + -g TckPin:PullUp \ + -g TdiPin:PullUp \ + -g TdoPin:PullUp \ + -g TmsPin:PullUp \ + -g UnusedPin:PullDown \ + -g UserID:0xFFFFFFFF \ + -g StartUpClk:CClk \ + -g DONE_cycle:4 \ + -g GTS_cycle:5 \ + -g GWE_cycle:6 \ + -g Security:None \ + -g DonePipe:No \ + -g Match_cycle:2 \ + -g DriveDone:No + +fpga_target: $(TARGET).bit + +$(TARGET).ngc: $(TARGET).xst $(VLOGS_ALL) + @mkdir -p xst/projnav.tmp + @echo work > $(TARGET).lso + @rm -f $(TARGET).prj + @for i in $(VLOGS); do echo verilog work '"'$$i'"' >> $(TARGET).prj; done + xst -ifn $(TARGET).xst -ofn $(TARGET).syr + +# for post-synth simulation +$(TARGET)-bare.ngc: $(TARGET)-bare.xst $(VLOGS_ALL) + @mkdir -p xst/projnav.tmp + @echo work > $(TARGET).lso + @rm -f $(TARGET).prj + @for i in $(VLOGS); do echo verilog work '"'$$i'"' >> $(TARGET).prj; done + xst -ifn $(TARGET)-bare.xst -ofn $(TARGET)-bare.syr + + +# for synth mismatch diagnostics +$(TARGET)-memory.ngc: $(TARGET)-memory.xst $(VLOGS_ALL) + @mkdir -p xst/projnav.tmp + @echo work > $(TARGET).lso + @rm -f $(TARGET).prj + @for i in $(VLOGS); do echo verilog work '"'$$i'"' >> $(TARGET).prj; done + xst -ifn $(TARGET)-memory.xst -ofn $(TARGET)-memory.syr + +sim/%.v: %.ngc + netgen -ofmt verilog -w -dir sim $< + +$(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf + ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc5vlx110t-ff1136-1 "$(TARGET).ngc" $(TARGET).ngd + +$(TARGET)_map.ncd: $(TARGET).ngd + map -w -p xc5vlx110t-ff1136-1 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf + +$(TARGET).ncd: $(TARGET)_map.ncd + par -w -ol std -t 1 $(TARGET)_map.ncd $(TARGET).ncd $(TARGET).pcf + +$(TARGET).twr: $(TARGET)_map.ncd + trce -e 3 -s 5 -xml $(TARGET) $(TARGET).ncd -o $(TARGET).twr $(TARGET).pcf -ucf $(TARGET).ucf + +$(TARGET).bit: $(TARGET).ncd + bitgen $(BITGEN_OPTS) $(TARGET).ncd + +$(TARGET).svf: $(TARGET).bit impact.cmd + sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd + impact -batch tmp.cmd + +clean: + rm -f $(TARGET).bgn $(TARGET).ngc $(TARGET).svf $(TARGET).ngd $(TARGET).bit $(TARGET).twr $(TARGET).ncd $(TARGET)_map.ncd $(TARGET)_map.* + rm -f $(TARGET).bld $(TARGET).drc $(TARGET)_ngdbuild.xrpt $(TARGET)_pad.* $(TARGET).pad $(TARGET).par $(TARGET)_par.xrpt $(TARGET).ngr + rm -f $(TARGET).pcf $(TARGET)_summary.xml $(TARGET).unroutes $(TARGET)_usage.xml $(TARGET)_xst.xrpt $(TARGET).syr $(TARGET).ptwx $(TARGET).xpi + rm -rf xst + rm -rf xlnx_auto_* + rm -rf _ngo + rm -f tmp.cmd + rm -f _impactbatch.log + rm -f $(TARGET).prj + rm -f $(TARGET).lso + diff --git a/xst/ibmpc1.mem b/xst/ibmpc1.mem new file mode 100644 index 0000000..221f4b7 --- /dev/null +++ b/xst/ibmpc1.mem @@ -0,0 +1,2050 @@ +01111110 +01000010 +01000010 +01000010 +01000010 +01000010 +01000010 +01111110 +01111110 +10000001 +10100101 +10000001 +10111101 +10011001 +10000001 +01111110 +01111110 +11111111 +11011011 +11111111 +11000011 +11100111 +11111111 +01111110 +01101100 +11111110 +11111110 +11111110 +01111100 +00111000 +00010000 +00000000 +00010000 +00111000 +01111100 +11111110 +01111100 +00111000 +00010000 +00000000 +00111000 +01111100 +00111000 +11111110 +11111110 +01111100 +00111000 +01111100 +00010000 +00010000 +00111000 +01111100 +11111110 +01111100 +00111000 +01111100 +00000000 +00000000 +00011000 +00111100 +00111100 +00011000 +00000000 +00000000 +11111111 +11111111 +11100111 +11000011 +11000011 +11100111 +11111111 +11111111 +00000000 +00111100 +01100110 +01000010 +01000010 +01100110 +00111100 +00000000 +11111111 +11000011 +10011001 +10111101 +10111101 +10011001 +11000011 +11111111 +00001111 +00000111 +00001111 +01111101 +11001100 +11001100 +11001100 +01111000 +00111100 +01100110 +01100110 +01100110 +00111100 +00011000 +01111110 +00011000 +00111111 +00110011 +00111111 +00110000 +00110000 +01110000 +11110000 +11100000 +01111111 +01100011 +01111111 +01100011 +01100011 +01100111 +11100110 +11000000 +10011001 +01011010 +00111100 +11100111 +11100111 +00111100 +01011010 +10011001 +10000000 +11100000 +11111000 +11111110 +11111000 +11100000 +10000000 +00000000 +00000010 +00001110 +00111110 +11111110 +00111110 +00001110 +00000010 +00000000 +00011000 +00111100 +01111110 +00011000 +00011000 +01111110 +00111100 +00011000 +01100110 +01100110 +01100110 +01100110 +01100110 +00000000 +01100110 +00000000 +01111111 +11011011 +11011011 +01111011 +00011011 +00011011 +00011011 +00000000 +00111110 +01100011 +00111000 +01101100 +01101100 +00111000 +11001100 +01111000 +00000000 +00000000 +00000000 +00000000 +01111110 +01111110 +01111110 +00000000 +00011000 +00111100 +01111110 +00011000 +01111110 +00111100 +00011000 +11111111 +00011000 +00111100 +01111110 +00011000 +00011000 +00011000 +00011000 +00000000 +00011000 +00011000 +00011000 +00011000 +01111110 +00111100 +00011000 +00000000 +00000000 +00011000 +00001100 +11111110 +00001100 +00011000 +00000000 +00000000 +00000000 +00110000 +01100000 +11111110 +01100000 +00110000 +00000000 +00000000 +00000000 +00000000 +11000000 +11000000 +11000000 +11111110 +00000000 +00000000 +00000000 +00100100 +01100110 +11111111 +01100110 +00100100 +00000000 +00000000 +00000000 +00011000 +00111100 +01111110 +11111111 +11111111 +00000000 +00000000 +00000000 +11111111 +11111111 +01111110 +00111100 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +00110000 +00110000 +00110000 +00110000 +00000000 +00110000 +00000000 +01101100 +01101100 +01101100 +00000000 +00000000 +00000000 +00000000 +00000000 +01101100 +01101100 +11111110 +01101100 +11111110 +01101100 +01101100 +00000000 +00110000 +01111100 +11000000 +01111000 +00001100 +11111000 +00110000 +00000000 +00000000 +11000110 +11001100 +00011000 +00110000 +01100110 +11000110 +00000000 +00111000 +01101100 +00111000 +01110110 +11011100 +11001100 +01110110 +00000000 +01100000 +01100000 +11000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011000 +00110000 +01100000 +01100000 +01100000 +00110000 +00011000 +00000000 +01100000 +00110000 +00011000 +00011000 +00011000 +00110000 +01100000 +00000000 +00000000 +01100110 +00111100 +11111111 +00111100 +01100110 +00000000 +00000000 +00000000 +00110000 +00110000 +11111100 +00110000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +00110000 +01100000 +00000000 +00000000 +00000000 +11111100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +00110000 +00000000 +00000110 +00001100 +00011000 +00110000 +01100000 +11000000 +10000000 +00000000 +01111100 +11000110 +11001110 +11011110 +11110110 +11100110 +01111100 +00000000 +00110000 +01110000 +00110000 +00110000 +00110000 +00110000 +11111100 +00000000 +01111000 +11001100 +00001100 +00111000 +01100000 +11001100 +11111100 +00000000 +01111000 +11001100 +00001100 +00111000 +00001100 +11001100 +01111000 +00000000 +00011100 +00111100 +01101100 +11001100 +11111110 +00001100 +00011110 +00000000 +11111100 +11000000 +11111000 +00001100 +00001100 +11001100 +01111000 +00000000 +00111000 +01100000 +11000000 +11111000 +11001100 +11001100 +01111000 +00000000 +11111100 +11001100 +00001100 +00011000 +00110000 +00110000 +00110000 +00000000 +01111000 +11001100 +11001100 +01111000 +11001100 +11001100 +01111000 +00000000 +01111000 +11001100 +11001100 +01111100 +00001100 +00011000 +01110000 +00000000 +00000000 +00110000 +00110000 +00000000 +00000000 +00110000 +00110000 +00000000 +00000000 +00110000 +00110000 +00000000 +00000000 +00110000 +00110000 +01100000 +00011000 +00110000 +01100000 +11000000 +01100000 +00110000 +00011000 +00000000 +00000000 +00000000 +11111100 +00000000 +00000000 +11111100 +00000000 +00000000 +01100000 +00110000 +00011000 +00001100 +00011000 +00110000 +01100000 +00000000 +01111000 +11001100 +00001100 +00011000 +00110000 +00000000 +00110000 +00000000 +01111100 +11000110 +11011110 +11011110 +11011110 +11000000 +01111000 +00000000 +00110000 +01111000 +11001100 +11001100 +11111100 +11001100 +11001100 +00000000 +11111100 +01100110 +01100110 +01111100 +01100110 +01100110 +11111100 +00000000 +00111100 +01100110 +11000000 +11000000 +11000000 +01100110 +00111100 +00000000 +11111000 +01101100 +01100110 +01100110 +01100110 +01101100 +11111000 +00000000 +01111110 +01100000 +01100000 +01111000 +01100000 +01100000 +01111110 +00000000 +01111110 +01100000 +01100000 +01111000 +01100000 +01100000 +01100000 +00000000 +00111100 +01100110 +11000000 +11000000 +11001110 +01100110 +00111110 +00000000 +11001100 +11001100 +11001100 +11111100 +11001100 +11001100 +11001100 +00000000 +01111000 +00110000 +00110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00011110 +00001100 +00001100 +00001100 +11001100 +11001100 +01111000 +00000000 +11100110 +01100110 +01101100 +01111000 +01101100 +01100110 +11100110 +00000000 +01100000 +01100000 +01100000 +01100000 +01100000 +01100000 +01111110 +00000000 +11000110 +11101110 +11111110 +11111110 +11010110 +11000110 +11000110 +00000000 +11000110 +11100110 +11110110 +11011110 +11001110 +11000110 +11000110 +00000000 +00111000 +01101100 +11000110 +11000110 +11000110 +01101100 +00111000 +00000000 +11111100 +01100110 +01100110 +01111100 +01100000 +01100000 +11110000 +00000000 +01111000 +11001100 +11001100 +11001100 +11011100 +01111000 +00011100 +00000000 +11111100 +01100110 +01100110 +01111100 +01101100 +01100110 +11100110 +00000000 +01111000 +11001100 +11100000 +01111000 +00011100 +11001100 +01111000 +00000000 +11111100 +00110000 +00110000 +00110000 +00110000 +00110000 +00110000 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +11001100 +11111100 +00000000 +11001100 +11001100 +11001100 +11001100 +11001100 +01111000 +00110000 +00000000 +11000110 +11000110 +11000110 +11010110 +11111110 +11101110 +11000110 +00000000 +11000110 +11000110 +01101100 +00111000 +00111000 +01101100 +11000110 +00000000 +11001100 +11001100 +11001100 +01111000 +00110000 +00110000 +01111000 +00000000 +11111110 +00000110 +00001100 +00011000 +00110000 +01100000 +11111110 +00000000 +01111000 +01100000 +01100000 +01100000 +01100000 +01100000 +01111000 +00000000 +11000000 +01100000 +00110000 +00011000 +00001100 +00000110 +00000010 +00000000 +01111000 +00011000 +00011000 +00011000 +00011000 +00011000 +01111000 +00000000 +00010000 +00111000 +01101100 +11000110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00110000 +00110000 +00011000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +11100000 +01100000 +01100000 +01111100 +01100110 +01100110 +11011100 +00000000 +00000000 +00000000 +01111000 +11001100 +11000000 +11001100 +01111000 +00000000 +00011100 +00001100 +00001100 +01111100 +11001100 +11001100 +01110110 +00000000 +00000000 +00000000 +01111000 +11001100 +11111100 +11000000 +01111000 +00000000 +00111000 +01101100 +01100000 +11110000 +01100000 +01100000 +11110000 +00000000 +00000000 +00000000 +01110110 +11001100 +11001100 +01111100 +00001100 +11111000 +11100000 +01100000 +01101100 +01110110 +01100110 +01100110 +11100110 +00000000 +00110000 +00000000 +01110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00001100 +00000000 +00001100 +00001100 +00001100 +11001100 +11001100 +01111000 +11100000 +01100000 +01100110 +01101100 +01111000 +01101100 +11100110 +00000000 +01110000 +00110000 +00110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00000000 +00000000 +11001100 +11111110 +11111110 +11010110 +11000110 +00000000 +00000000 +00000000 +11111000 +11001100 +11001100 +11001100 +11001100 +00000000 +00000000 +00000000 +01111000 +11001100 +11001100 +11001100 +01111000 +00000000 +00000000 +00000000 +11011100 +01100110 +01100110 +01111100 +01100000 +11110000 +00000000 +00000000 +01110110 +11001100 +11001100 +01111100 +00001100 +00011110 +00000000 +00000000 +11011100 +01110110 +01100110 +01100000 +11110000 +00000000 +00000000 +00000000 +01111100 +11000000 +01111000 +00001100 +11111000 +00000000 +00010000 +00110000 +01111100 +00110000 +00110000 +00110100 +00011000 +00000000 +00000000 +00000000 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00000000 +00000000 +11001100 +11001100 +11001100 +01111000 +00110000 +00000000 +00000000 +00000000 +11000110 +11010110 +11111110 +11111110 +01101100 +00000000 +00000000 +00000000 +11000110 +01101100 +00111000 +01101100 +11000110 +00000000 +00000000 +00000000 +11001100 +11001100 +11001100 +01111100 +00001100 +11111000 +00000000 +00000000 +11111100 +10011000 +00110000 +01100100 +11111100 +00000000 +00011100 +00110000 +00110000 +11100000 +00110000 +00110000 +00011100 +00000000 +00011000 +00011000 +00011000 +00000000 +00011000 +00011000 +00011000 +00000000 +11100000 +00110000 +00110000 +00011100 +00110000 +00110000 +11100000 +00000000 +01110110 +11011100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010000 +00111000 +01101100 +11000110 +11111110 +00000000 +00000000 +00111100 +01100110 +11000000 +11000000 +01100110 +00111100 +00001000 +00011000 +00101000 +00000000 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00001000 +00010000 +01111000 +11001100 +11111100 +11000000 +01111000 +00000000 +00010000 +00101000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +00101000 +00000000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +00100000 +00010000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +00011000 +00011000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +00000000 +01111000 +11001100 +11000000 +11001100 +01111000 +00010000 +00110000 +00010000 +00101000 +01111000 +11001100 +11111100 +11000000 +01111000 +00000000 +00101000 +00000000 +01111000 +11001100 +11111100 +11000000 +01111000 +00000000 +00100000 +00010000 +01111000 +11001100 +11111100 +11000000 +01111000 +00000000 +00101000 +00000000 +01110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00010000 +00101000 +01110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00010000 +00001000 +01110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00101000 +00110000 +01111000 +11001100 +11111100 +11001100 +11001100 +00000000 +00110000 +01001000 +00110000 +11001100 +11111100 +11001100 +11001100 +00000000 +00001000 +00010000 +01111110 +01100000 +01111000 +01100000 +01111110 +00000000 +00000000 +00000000 +01101100 +00010010 +01111110 +10010000 +01111110 +00000000 +00111110 +01010000 +10010000 +10011100 +11110000 +10010000 +10011110 +00000000 +00010000 +00101000 +01111000 +11001100 +11001100 +11001100 +01111000 +00000000 +00101000 +00000000 +01111000 +11001100 +11001100 +11001100 +01111000 +00000000 +00100000 +00010000 +01111000 +11001100 +11001100 +11001100 +01111000 +00000000 +00010000 +00101000 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00100000 +00010000 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00101000 +00000000 +11001100 +11001100 +11001100 +01111100 +00001100 +11111000 +00101000 +01111100 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00101000 +11000110 +11000110 +11000110 +11000110 +11000110 +01111100 +00000000 +00000000 +00010000 +01111000 +11001100 +11000000 +11001100 +01111000 +00010000 +00111000 +01000100 +01000000 +11110000 +01000000 +01000000 +11111110 +00000000 +11000011 +01100110 +00111100 +01111110 +00011000 +01111110 +00011000 +00000000 +11111100 +01100110 +01100110 +01111100 +01100000 +01100000 +11110000 +00000000 +00011100 +00110000 +11111100 +00110000 +00110000 +00110000 +00110000 +11100000 +00001000 +00010000 +01111000 +00001100 +01111100 +11001100 +01110110 +00000000 +00010000 +00100000 +01110000 +00110000 +00110000 +00110000 +01111000 +00000000 +00010000 +00100000 +01111000 +11001100 +11001100 +11001100 +01111000 +00000000 +00010000 +00100000 +11001100 +11001100 +11001100 +11001100 +01110110 +00000000 +00110010 +01001100 +11111000 +11001100 +11001100 +11001100 +11001100 +00000000 +00110010 +01001100 +11000110 +11100110 +11010110 +11001110 +11000110 +00000000 +00000000 +00111000 +00001100 +00111100 +01101100 +00110110 +00000000 +00000000 +00000000 +00111000 +01000100 +01000100 +00111000 +00000000 +00000000 +00000000 +00011000 +00000000 +00011000 +00110000 +01100000 +01100110 +00111100 +00000000 +00000000 +00000000 +11111110 +10000000 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000010 +00000010 +00000000 +00000000 +00000000 +01000010 +01000100 +01001000 +01010110 +00101001 +01000110 +10001000 +00011111 +01000010 +01000100 +01001000 +01010110 +00101010 +01011111 +10000010 +00000111 +00110000 +00000000 +00110000 +00110000 +00110000 +00110000 +00110000 +00000000 +00000000 +00100100 +01001000 +10010000 +01001000 +00100100 +00000000 +00000000 +00000000 +01001000 +00100100 +00010010 +00100100 +01001000 +00000000 +00000000 +10001000 +00100010 +10001000 +00100010 +10001000 +00000000 +10001000 +00100010 +10101010 +01010101 +10101010 +01010101 +10101010 +00000000 +10101010 +01010101 +01110111 +11011101 +01110111 +11011101 +01110111 +11111111 +01110111 +11011101 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +11110000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +11110000 +00010000 +11110000 +00010000 +00010000 +00010000 +00101000 +00101000 +00101000 +11101000 +00101000 +00101000 +00101000 +00101000 +00000000 +00000000 +00000000 +11111000 +00101000 +00101000 +00101000 +00101000 +00000000 +00000000 +11110000 +00010000 +11110000 +00010000 +00010000 +00010000 +00101000 +00101000 +11101000 +00001000 +11101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00000000 +00000000 +11111000 +00001000 +11101000 +00101000 +00101000 +00101000 +00101000 +00101000 +11101000 +00001000 +11111000 +00000000 +00000000 +00000000 +00101000 +00101000 +00101000 +11111000 +00000000 +00000000 +00000000 +00000000 +00010000 +00010000 +11110000 +00010000 +11110000 +00000000 +00000000 +00000000 + +00000000 +0000000 +00000000 +11110000 +00010000 +00010000 +00010000 +00010000 + +0010000 +00010000 +00010000 +00011111 +00000000 +00000000 +00000000 +00000000 +00010000 +00010000 +00010000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00011111 +00010000 +00010000 +00010000 +00010000 +00000000 +00000000 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00010000 +00010000 +00010000 +11111111 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00011111 +00010000 +00011111 +00010000 +00010000 +00010000 +00101000 +00101000 +00101000 +00101111 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101111 +00100000 +00111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00111111 +00100000 +00101111 +00101000 +00101000 +00101000 +00101000 +00101000 +11101111 +00000000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +11101111 +00101000 +00101000 +00101000 +00101000 +00101000 +00101111 +00100000 +00101111 +00101000 +00101000 +00101000 +00000000 +00000000 +11111111 +00000000 +11111111 +00000000 +00000000 +00000000 +00101000 +00101000 +11101111 +00000000 +11101111 +00101000 +00101000 +00101000 +00010000 +00010000 +11111111 +00000000 +11111111 +00000000 +00000000 +00000000 +00101000 +00101000 +00101000 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +00000000 +11111111 +00010000 +00010000 +00010000 +00000000 +00000000 +00000000 +11111111 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00111111 +00000000 +00000000 +00000000 +00000000 +00010000 +00010000 +00011111 +00010000 +00011111 +00000000 +00000000 +00000000 +00000000 +00000000 +00011111 +00010000 +00011111 +00010000 +00010000 +00010000 +00000000 +00000000 +00000000 +00111111 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +00101000 +11111111 +00101000 +00101000 +00101000 +00101000 +00010000 +00010000 +11111111 +00010000 +11111111 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +11110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00011111 +00010000 +00010000 +00010000 +00010000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00000000 +00000000 +00000000 +11111111 +11111111 +11111111 +11111111 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +11110000 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +00001111 +11111111 +11111111 +11111111 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01110010 +10001100 +10001000 +0111010 +00000000 +00110000 +01001000 +01001000 +01111100 +01000010 +01000010 +11011100 +00000000 +00000000 +00000000 +11111110 +01000010 +01000000 +01000000 +11100000 +00000000 +00000000 +00000000 +11111110 +01000100 +01000100 +01000100 +11101110 +00000000 +11111110 +01000010 +00100000 +00010000 +00100000 +01000010 +11111110 +00000000 +00000000 +00000000 +00000000 +00111110 +01000100 +01000100 +00111000 +00000000 +00000000 +00000000 +11001100 +01000100 +01000100 +01000100 +01111010 +01000000 +00000000 +00000000 +01111100 +00010000 +00010000 +00010000 +00011100 +00000000 +00000000 +00010000 +01111100 +10010010 +10010010 +01111100 +00010000 +00000000 +00000000 +00000000 +01111100 +10000010 +10111010 +10000010 +01111100 +00000000 +00000000 +01111100 +10000010 +10000010 +01101100 +00101000 +11101110 +00000000 +00000000 +01111100 +00100000 +00111000 +01000100 +01000100 +00111000 +00000000 +00000000 +00000000 +01101100 +10010010 +10010010 +01101100 +00000000 +00000000 +00000000 +00000000 +01001100 +10010010 +10010010 +01111100 +00010000 +00000000 +00000000 +00000000 +00111100 +01000000 +00110000 +01000000 +00111100 +00000000 +00000000 +00000000 +00111100 +01000010 +01000010 +01000010 +01000010 +00000000 +00000000 +11111110 +00000000 +11111110 +00000000 +11111110 +00000000 +00000000 +00010000 +00010000 +11111110 +00010000 +00010000 +11111110 +00000000 +00000000 +01000000 +00010000 +00000100 +00010000 +01000000 +11111110 +00000000 +00000000 +00000100 +00010000 +01000000 +00010000 +00000100 +11111110 +00000000 +00000000 +00001100 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +00010000 +01100000 +00000000 +00000000 +00010000 +00000000 +11111110 +00000000 +00010000 +00000000 +00000000 +01100010 +10011100 +00000000 +01100010 +10011100 +00000000 +00000000 +00110000 +01001000 +01001000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110000 +00110000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00001000 +00000000 +00000000 +00000000 +00000001 +00000010 +11100010 +00100100 +00010100 +00011000 +00001000 +00000000 +00000000 +00000000 +01011000 +00100100 +00100100 +00000000 +00000000 +00000000 +00110000 +01001000 +00010000 +00100000 +01111000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111111 +11111111 +11111111 +11111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/xst/iic_init.v b/xst/iic_init.v new file mode 100644 index 0000000..60fe281 --- /dev/null +++ b/xst/iic_init.v @@ -0,0 +1,219 @@ +`timescale 1 ns / 100 ps +module iic_init( Clk, //I + Reset_n, //I + Pixel_clk_greater_than_65Mhz, //I + SDA, //IO + SCL, //IO + Done //O + ); + +input Clk; +input Reset_n; +input Pixel_clk_greater_than_65Mhz; +inout SDA; +inout SCL; +output Done; + +parameter CLK_RATE_MHZ = 200, + SCK_PERIOD_US = 30, + TRANSITION_CYCLE = (CLK_RATE_MHZ * SCK_PERIOD_US) / 2, + TRANSITION_CYCLE_MSB = 11; + + +localparam IDLE = 3'd0, + INIT = 3'd1, + START = 3'd2, + CLK_FALL = 3'd3, + SETUP = 3'd4, + CLK_RISE = 3'd5, + WAIT = 3'd6, + START_BIT = 1'b1, + SLAVE_ADDR= 7'b1110110, + ACK = 1'b1, + WRITE = 1'b0, + REG_ADDR0 = 8'h49, + REG_ADDR1 = 8'h21, + REG_ADDR2 = 8'h33, + REG_ADDR3 = 8'h34, + REG_ADDR4 = 8'h36, + DATA0 = 8'hC0, + DATA1 = 8'h09, + DATA2a = 8'h06, + DATA3a = 8'h26, + DATA4a = 8'hA0, + DATA2b = 8'h08, + DATA3b = 8'h16, + DATA4b = 8'h60, + STOP_BIT=1'b0, + SDA_BUFFER_MSB=27; + +reg SDA_out; +reg SCL_out; +reg [TRANSITION_CYCLE_MSB:0] cycle_count; +reg [2:0] c_state; +reg [2:0] n_state; +reg Done; +reg [2:0] write_count; +reg [31:0] bit_count; +reg [SDA_BUFFER_MSB:0] SDA_BUFFER; +wire transition; + +always @ (posedge Clk) begin + if (~Reset_n||c_state==IDLE ) begin + SDA_out <= 1'b1; + SCL_out <=1'b1; + end + else if (c_state==INIT && transition) begin + SDA_out <=1'b0; + end + else if (c_state==SETUP) begin + SDA_out <=SDA_BUFFER[SDA_BUFFER_MSB]; + end + else if (c_state==CLK_RISE && cycle_count==TRANSITION_CYCLE/2 && bit_count==SDA_BUFFER_MSB) begin + SDA_out <= 1'b1; + end + else if (c_state==CLK_FALL) begin + SCL_out <=1'b0; + end + + else if (c_state==CLK_RISE) begin + SCL_out <=1'b1; + end +end + +//OBUFT_LVCMOS33 sda0(.O(SDA), .I(1'b0), .T(SDA_out)); +//OBUFT_LVCMOS33 scl0(.O(SCL), .I(1'b0), .T(SCL_out)); +assign SDA = SDA_out; +assign SCL = SCL_out; + +always @ (posedge Clk) begin + //reset or end condition + if(~Reset_n) begin + SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR0,ACK,DATA0,ACK,STOP_BIT}; + cycle_count<=0; + + end + //setup sda for sck rise + else if ( c_state==SETUP && cycle_count==TRANSITION_CYCLE)begin + SDA_BUFFER <= {SDA_BUFFER[SDA_BUFFER_MSB-1:0],1'b0}; + cycle_count<=0; + end + //reset count at end of state + else if ( cycle_count==TRANSITION_CYCLE) + cycle_count<=0; + //reset sda_buffer + else if (c_state==WAIT && Pixel_clk_greater_than_65Mhz )begin + case(write_count) + 0:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR1,ACK,DATA1,ACK,STOP_BIT}; + 1:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR2,ACK,DATA2a,ACK,STOP_BIT}; + 2:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR3,ACK,DATA3a,ACK,STOP_BIT}; + 3:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR4,ACK,DATA4a,ACK,STOP_BIT}; + default: SDA_BUFFER <=28'dx; + endcase + cycle_count<=cycle_count+1; + + end + else if (c_state==WAIT && ~Pixel_clk_greater_than_65Mhz )begin + case(write_count) + 0:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR1,ACK,DATA1,ACK,STOP_BIT}; + 1:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR2,ACK,DATA2b,ACK,STOP_BIT}; + 2:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR3,ACK,DATA3b,ACK,STOP_BIT}; + 3:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR4,ACK,DATA4b,ACK,STOP_BIT}; + default: SDA_BUFFER <=28'dx; + endcase + cycle_count<=cycle_count+1; + end + else + cycle_count<=cycle_count+1; +end + +always @ (posedge Clk) begin + if(~Reset_n) + write_count<=3'd0; + else if (c_state==WAIT && cycle_count==TRANSITION_CYCLE) + write_count<=write_count+1; +end + + +always @ (posedge Clk) begin + if(~Reset_n) + Done<=1'b0; + else if (c_state==IDLE) + Done<=1'b1; +end + + + + +always @ (posedge Clk) begin + if(~Reset_n||(c_state==WAIT)) + bit_count<=0; + else if ( c_state==CLK_RISE && cycle_count==TRANSITION_CYCLE) + bit_count<=bit_count+1; +end + + + +always @ (posedge Clk) begin + if(~Reset_n) + c_state<=INIT; + else + c_state<=n_state; +end + + + +assign transition = (cycle_count==TRANSITION_CYCLE); + +//Next state +always @ (*) begin + case(c_state) + IDLE: begin + if(~Reset_n) n_state = INIT; + else n_state = IDLE; + end + INIT: begin + if (transition) n_state = START; + else n_state = INIT; + end + START: begin + if(~Reset_n) n_state = INIT; + else if( transition) n_state = CLK_FALL; + else n_state = START; + end + CLK_FALL: begin + if(~Reset_n) n_state = INIT; + else if( transition) n_state = SETUP; + else n_state = CLK_FALL; + end + SETUP: begin + if(~Reset_n) n_state = INIT; + else if( transition) n_state = CLK_RISE; + else n_state = SETUP; + end + CLK_RISE: begin + if(~Reset_n) + n_state = INIT; + else if( transition && bit_count==SDA_BUFFER_MSB) + n_state = WAIT; + else if (transition ) + n_state = CLK_FALL; + else n_state = CLK_RISE; + end + WAIT: begin + if(~Reset_n|(transition && write_count!=3'd4)) + n_state = INIT; + else if (transition ) + n_state = IDLE; + else n_state = WAIT; + end + default: n_state = IDLE; + + endcase +end + + + + + +endmodule diff --git a/xst/impact.cmd b/xst/impact.cmd new file mode 100644 index 0000000..752fa2b --- /dev/null +++ b/xst/impact.cmd @@ -0,0 +1,7 @@ +setMode -bs +setCable -port svf -file "XXX.svf" +addDevice -p 1 -file "XXX.bit" +addDevice -p 2 -part xcf04s +Program -p 1 -defaultVersion 0 +quit + diff --git a/xst/ram.hex b/xst/ram.hex new file mode 120000 index 0000000..7e6fff8 --- /dev/null +++ b/xst/ram.hex @@ -0,0 +1 @@ +../tests/testbench.pad.hex \ No newline at end of file diff --git a/xst/scancodes.shifted.hex b/xst/scancodes.shifted.hex new file mode 100644 index 0000000..5c16b6b --- /dev/null +++ b/xst/scancodes.shifted.hex @@ -0,0 +1,128 @@ +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +09 +7E +0 +0 +0 +0 +0 +0 +51 +21 +0 +0 +0 +5A +53 +41 +57 +40 +0 +0 +43 +58 +44 +45 +24 +23 +0 +0 +20 +56 +46 +54 +52 +25 +0 +0 +4E +42 +48 +47 +59 +5E +0 +0 +0 +4D +4A +55 +26 +2A +0 +0 +3C +4B +49 +4F +29 +28 +0 +0 +2C +3F +4C +3A +50 +5F +0 +0 +0 +22 +0 +7B +2B +0 +0 +0 +0 +0A +7D +0 +7C +0 +0 +0 +0 +0 +0 +0 +0 +08 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1B +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/xst/scancodes.unshifted.hex b/xst/scancodes.unshifted.hex new file mode 100644 index 0000000..b860bdb --- /dev/null +++ b/xst/scancodes.unshifted.hex @@ -0,0 +1,128 @@ +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +09 +60 +0 +0 +0 +0 +0 +0 +71 +31 +0 +0 +0 +7A +73 +61 +77 +32 +0 +0 +63 +78 +64 +65 +34 +33 +0 +0 +20 +76 +66 +74 +72 +35 +0 +0 +6E +62 +68 +67 +79 +36 +0 +0 +0 +6D +6A +75 +37 +38 +0 +0 +2C +6B +69 +6F +30 +39 +0 +0 +2E +2F +6C +3B +70 +2D +0 +0 +0 +27 +0 +5B +3D +0 +0 +0 +0 +0A +5D +0 +5C +0 +0 +0 +0 +0 +0 +0 +0 +08 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1B +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/xst/sim/tb.v b/xst/sim/tb.v new file mode 100644 index 0000000..b325713 --- /dev/null +++ b/xst/sim/tb.v @@ -0,0 +1,15 @@ +`timescale 1 ns/1 ps + +module tb(); + reg clk = 0; + wire [8:0] odata; + + System system(.clk(clk), .rst(1'b0), .sys_odata(odata), .sys_idata(9'b0), .sys_tookdata(tookdata)); + glbl glbl(); + + initial begin + $monitor($stime,,"odata: %x = %c", odata, odata[7:0]); + while(1) + #30 clk <= ~clk; + end +endmodule -- 2.39.2