From 804dc0bc2463fcb61a67c3f8da271bedd131a80c Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sat, 10 Jan 2009 00:51:00 -0500 Subject: [PATCH] Memory: wire -> reg in some cases --- Memory.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Memory.v b/Memory.v index eb4006f..241c50a 100644 --- a/Memory.v +++ b/Memory.v @@ -23,7 +23,7 @@ module Memory( output reg cp_req, input cp_ack, input cp_busy, - output cp_rnw, /* 1 = read from CP, 0 = write to CP */ + output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */ input [31:0] cp_read, output reg [31:0] cp_write, @@ -57,10 +57,10 @@ module Memory( reg [3:0] next_regsel, cur_reg, prev_reg; reg next_writeback; - wire next_outbubble; - wire next_write_reg; - wire [3:0] next_write_num; - wire [31:0] next_write_data; + reg next_outbubble; + reg next_write_reg; + reg [3:0] next_write_num; + reg [31:0] next_write_data; reg [1:0] lsr_state = 2'b01, next_lsr_state; reg [31:0] align_s1, align_s2, align_rddata; -- 2.39.2