From 7947b9c731a2c981f1a32d2f8f47ab42464e7b17 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Mon, 5 Jan 2009 05:26:19 -0500 Subject: [PATCH] Ok, it work. --- Execute.v | 8 ++++---- Issue.v | 2 +- ram.comments.hex | Bin 1307 -> 1307 bytes ram.hex | Bin 594 -> 594 bytes system.v | 9 ++++----- 5 files changed, 9 insertions(+), 10 deletions(-) diff --git a/Execute.v b/Execute.v index 4e3f44f..8a7d8f6 100644 --- a/Execute.v +++ b/Execute.v @@ -163,12 +163,12 @@ module Execute( begin end `DECODE_BRANCH: begin - if(!prevstall && !inbubble) begin + if(!inbubble) begin jmppc = pc + op0 + 32'h8; if(insn[24]) begin next_write_reg = 1; next_write_num = 4'hE; /* link register */ - next_write_data = pc + 32'h4; + next_write_data = pc - 32'h4; end jmp = 1'b1; end @@ -236,8 +236,8 @@ module ALU( output reg [31:0] cpsr_out, output reg setres ); - wire [31:0] res; - wire flag_n, flag_z, flag_c, flag_v, setres; + reg [31:0] res; + reg flag_n, flag_z, flag_c, flag_v; wire [32:0] sum, diff, rdiff; wire sum_v, diff_v, rdiff_v; diff --git a/Issue.v b/Issue.v index a6b7109..7b281a3 100644 --- a/Issue.v +++ b/Issue.v @@ -282,7 +282,7 @@ module Issue( waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); - outstall = (waiting && !inbubble) || stall; /* Happens in an always @*, because it is an exception. */ + outstall = ((waiting && !inbubble) || stall) && !flush; /* Happens in an always @*, because it is an exception. */ end /* Actually do the issue. */ diff --git a/ram.comments.hex b/ram.comments.hex index bffc93bef7cb0c897af19e21d78981cdb4222b7b..b1fa9508b8653e740ad32513f41b749c80b87a9b 100644 GIT binary patch delta 26 fcmbQuHJfWg5;MD_8wj{g&SbV?bl$v#xttLIX>kXd delta 26 ecmbQuHJfWg5;MD#8yHN^WVT{-*}R0goDl$Nl?R;w diff --git a/ram.hex b/ram.hex index 9f19cbb64c190c7ee81a557755b2397d9b4a93ad..1a068cc6efbd76e0538079a045e90b19ec1342da 100644 GIT binary patch delta 41 ocmcb_a*1Wa1xZIY5OC#kHFPup0WMc3u!!?!Lq}mefXik>Mn%TS3XC2A16&I7 diff --git a/system.v b/system.v index f80f327..4601ae7 100644 --- a/system.v +++ b/system.v @@ -54,9 +54,7 @@ module System(input clk); wire [31:0] pc_out_fetch; wire [31:0] pc_out_issue; - wire execute_outflush = jmp; - wire issue_flush = execute_outflush; - wire execute_flush = 1'b0; + wire execute_out_backflush; BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack)); @@ -88,7 +86,7 @@ module System(input clk); Issue issue( .clk(clk), .Nrst(1'b1 /* XXX */), - .stall(stall_cause_execute), .flush(issue_flush), + .stall(stall_cause_execute), .flush(execute_out_backflush), .inbubble(bubble_out_fetch), .insn(insn_out_fetch), .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */), .outstall(stall_cause_issue), .outbubble(bubble_out_issue), @@ -110,7 +108,7 @@ module System(input clk); Execute execute( .clk(clk), .Nrst(1'b0), - .stall(1'b0 /* XXX */), .flush(execute_flush), + .stall(1'b0 /* XXX */), .flush(1'b0), .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue), .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2), .carry(decode_out_carry), @@ -119,6 +117,7 @@ module System(input clk); .write_data(execute_out_write_data), .jmppc(jmppc), .jmp(jmp)); + assign execute_out_backflush = jmp; reg [31:0] clockno = 0; always @(posedge clk) -- 2.43.0