From 74d3729c44271277d935b105d5b1028510a23192 Mon Sep 17 00:00:00 2001
From: Christopher Lu <lu@stop.hsd1.pa.comcast.net>
Date: Tue, 6 Jan 2009 01:34:42 -0500
Subject: [PATCH] memory: fixed up a bit

---
 Memory.v | 86 +++++++++++++++++++++++---------------------------------
 1 file changed, 35 insertions(+), 51 deletions(-)

diff --git a/Memory.v b/Memory.v
index 2b4b2a4..c4cee4d 100644
--- a/Memory.v
+++ b/Memory.v
@@ -31,14 +31,16 @@ module Memory(
 
 	/* stall */
 	output outstall,
-	output reg outbubble,
-	output reg flush
+	output reg outbubble
 );
 
-	reg [31:0] addr, raddr;
+	reg [31:0] addr, raddr, next_regdata, next_newpc;
+	reg [3:0] next_regsel;
+	reg next_writeback, next_notdone, next_inc_next;
+	reg [31:0] align_s1, align_s2, align_rddata;
+
 	reg notdone = 1'b0;
 	reg inc_next = 1'b0;
-	wire [31:0] align_s1, align_s2, align_rddata;
 	assign outstall = rw_wait | notdone;
 
 	always @(*)
@@ -50,6 +52,11 @@ module Memory(
 		wr_data = 32'hxxxxxxxx;
 		busaddr = 32'hxxxxxxxx;
 		outstall = 1'b0;
+		next_notdone = 1'b0;
+		next_regsel = 4'hx;
+		next_regdata = 32'hxxxxxxxx;
+		next_inc_next = 1'b0;
+		next_newpc = 32'hxxxxxxxx;
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
@@ -58,12 +65,27 @@ module Memory(
 			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
 			rd_req = insn[20];
 			wr_req = ~insn[20];
-			if(!insn[20]) begin /* store */
+
+			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+
+			if(!insn[20]) begin
 				st_read = insn[15:12];
 				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
 			end
-			else if(insn[15:12] == 4'hF)
-				flush = 1'b1;
+			else if(!inc_next) begin /* store */
+				next_writeback = 1'b1;
+				next_regsel = insn[15:12];
+				next_regdata = align_rddata;
+				next_inc_next = 1'b1;
+			end
+			else if(insn[21]) begin
+				next_writeback = 1'b1;
+				next_regsel = insn[19:16];
+				next_regdata = addr;
+			end
+			next_notdone = rw_wait & insn[20] & insn[21];
 		end
 		`DECODE_LDMSTM: begin
 		end
@@ -71,55 +93,17 @@ module Memory(
 		endcase
 	end
 
-	assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-	assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-	assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 
 	always @(posedge clk)
 	begin
 		outpc <= pc;
 		outbubble <= rw_wait;
-		casez(insn)
-		`DECODE_LDRSTR_UNDEFINED: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
-		`DECODE_LDRSTR: begin
-			if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
-				if(insn[15:12] == 4'hF) begin
-					newpc <= align_rddata;
-				end
-				else begin
-					writeback <= 1'b1;
-					regsel <= insn[15:12];
-					regdata <= align_rddata;
-				end
-				inc_next <= 1'b1;
-			end
-			else if(insn[21]) begin /* write back */
-				writeback <= 1'b1;
-				regsel <= insn[19:16];
-				regdata <= addr;
-				inc_next <= 1'b0;
-			end else begin
-				writeback <= 1'b0;
-				inc_next <= 1'b0;
-				regsel <= 4'hx;
-				regdata <= 32'hxxxxxxxx;
-			end
-			notdone <= rw_wait & insn[20] & insn[21];
-		end
-		`DECODE_LDMSTM: begin
-		end
-		default: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
-		endcase
+		writeback <= next_writeback;
+		regsel <= next_regsel;
+		regdata <= next_regdata;
+		notdone <= next_notdone;
+		newpc <= next_newpc;
+		inc_next <= next_inc_next;
 	end
 
 endmodule
-- 
2.39.2