From 326fd4c33d4331252af93af8ee3fe5dbb7ff0d3f Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sat, 27 Dec 2008 20:50:09 -0500 Subject: [PATCH 1/1] Ok, move read_0, read_1, read_2 back into a unified block again. --- Decode.v | 107 ++++++++++++++++++------------------------------------- 1 file changed, 35 insertions(+), 72 deletions(-) diff --git a/Decode.v b/Decode.v index 2698eca..fd8554b 100644 --- a/Decode.v +++ b/Decode.v @@ -63,109 +63,72 @@ module Decode( rpc = 32'hxxxxxxxx; endcase - always @(*) + always @(*) begin + read_0 = 4'hx; + read_1 = 4'hx; + read_2 = 4'hx; + casez (insn) 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ + begin read_0 = insn[15:12]; /* Rn */ + read_1 = insn[3:0]; /* Rm */ + read_2 = insn[11:8]; /* Rs */ + end // 32'b????00001???????????????1001????, /* Multiply long */ // read_0 = insn[11:8]; /* Rn */ +// read_1 = insn[3:0]; /* Rm */ +// read_2 = 4'b0; /* anyus */ 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */ 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */ 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */ - read_0 = 4'hx; + begin end /* Everything stays x'ed out. */ 32'b????00??????????????????????????: /* ALU */ + begin read_0 = insn[19:16]; /* Rn */ + read_1 = insn[3:0]; /* Rm */ + read_2 = insn[11:8]; /* Rs for shift */ + end 32'b????00010?00????????00001001????: /* Atomic swap */ + begin read_0 = insn[19:16]; /* Rn */ + read_1 = insn[3:0]; /* Rm */ + end 32'b????000100101111111111110001????: /* Branch and exchange */ read_0 = insn[3:0]; /* Rn */ 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */ + begin read_0 = insn[19:16]; - 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */ + read_1 = insn[3:0]; + end + 32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */ + begin read_0 = insn[19:16]; + read_1 = insn[3:0]; + end 32'b????011????????????????????1????: /* Undefined. I hate ARM */ - read_0 = 4'hx; + begin end 32'b????01??????????????????????????: /* Single data transfer */ + begin read_0 = insn[19:16]; /* Rn */ + read_1 = insn[3:0]; /* Rm */ + end 32'b????100?????????????????????????: /* Block data transfer */ read_0 = insn[19:16]; 32'b????101?????????????????????????: /* Branch */ - read_0 = 4'hx; + begin end 32'b????110?????????????????????????: /* Coprocessor data transfer */ read_0 = insn[19:16]; 32'b????1110???????????????????0????, /* Coprocessor data op */ 32'b????1110???????????????????1????, /* Coprocessor register transfer */ 32'b????1111????????????????????????: /* SWI */ - read_0 = 4'hx; + begin end default: - read_0 = 4'hx; - endcase - - always @(*) - casez (insn) - 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ - read_1 = insn[3:0]; /* Rm */ -// 32'b????00001???????????????1001????: /* Multiply long */ -// read_1 = insn[3:0]; /* Rm */ - 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */ - 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */ - 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */ - read_1 = 4'hx; - 32'b????00??????????????????????????: /* ALU */ - read_1 = insn[3:0]; /* Rm */ - 32'b????00010?00????????00001001????: /* Atomic swap */ - read_1 = insn[3:0]; /* Rm */ - 32'b????000100101111111111110001????: /* Branch and exchange */ - read_1 = 4'hx; - 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */ - read_1 = insn[3:0]; - 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */ - read_1 = insn[3:0]; - 32'b????011????????????????????1????: /* Undefined. I hate ARM */ - read_1 = 4'hx; - 32'b????01??????????????????????????: /* Single data transfer */ - read_1 = insn[3:0]; /* Rm */ - 32'b????100?????????????????????????, /* Block data transfer */ - 32'b????101?????????????????????????, /* Branch */ - 32'b????110?????????????????????????, /* Coprocessor data transfer */ - 32'b????1110???????????????????0????, /* Coprocessor data op */ - 32'b????1110???????????????????1????, /* Coprocessor register transfer */ - 32'b????1111????????????????????????: /* SWI */ - read_1 = 4'hx; - default: - read_1 = 4'hx; + $display("Undecoded instruction"); endcase + end - always @(*) - casez (insn) - 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ - read_2 = insn[11:8]; /* Rs */ -// 32'b????00001???????????????1001????: /* Multiply long */ -// read_2 = 4'b0; /* anyus */ - 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */ - 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */ - 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */ - read_2 = 4'hx; - 32'b????00??????????????????????????: /* ALU */ - read_2 = insn[11:8]; /* Rs for shift */ - 32'b????00010?00????????00001001????, /* Atomic swap */ - 32'b????000100101111111111110001????, /* Branch and exchange */ - 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */ - 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */ - 32'b????011????????????????????1????, /* Undefined. I hate ARM */ - 32'b????01??????????????????????????, /* Single data transfer */ - 32'b????100?????????????????????????, /* Block data transfer */ - 32'b????101?????????????????????????, /* Branch */ - 32'b????110?????????????????????????, /* Coprocessor data transfer */ - 32'b????1110???????????????????0????, /* Coprocessor data op */ - 32'b????1110???????????????????1????, /* Coprocessor register transfer */ - 32'b????1111????????????????????????: /* SWI */ - read_2 = 4'hx; - default: - read_2 = 4'hx; - endcase - - always @ (*) begin + always @(*) begin op1_res = 32'hxxxxxxxx; cpsr = 32'hxxxxxxxx; casez (insn) -- 2.39.2