From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 7 Jan 2009 09:58:34 +0000 (-0500)
Subject: Add special CPSR behavior for ARM MCR.
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/d1d0eb8e5614d620d5a62713ed11c0e34470f64e?hp=e9bde5ae66fd6ee69b04b54280e9cbd32ab6c9d2

Add special CPSR behavior for ARM MCR.
---

diff --git a/Memory.v b/Memory.v
index c735ed9..ff9f397 100644
--- a/Memory.v
+++ b/Memory.v
@@ -325,9 +325,12 @@ module Memory(
 			if (insn[20] == 0 /* store to coprocessor */)
 				cp_write = op0;
 			else begin
-				next_write_reg = 1'b1;
-				next_write_num = insn[15:12];
-				next_write_data = cp_read;
+				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[15:12];
+					next_write_data = cp_read;
+				end else
+					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
 			end
 			if (cp_busy) begin
 				outstall = 1;