From: Joshua Wise Date: Tue, 6 Jan 2009 08:15:58 +0000 (-0500) Subject: Wire in Memory. Fix small bug in Memory involving registers never ever getting outpu... X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/c65110a8c83463c0f95391c2ec7e0277de333c62 Wire in Memory. Fix small bug in Memory involving registers never ever getting output (type A...). --- diff --git a/Execute.v b/Execute.v index cd71d76..7f4cf6c 100644 --- a/Execute.v +++ b/Execute.v @@ -25,7 +25,8 @@ module Execute( output reg [31:0] jmppc, output reg jmp, output reg [31:0] outpc, - output reg [31:0] outinsn + output reg [31:0] outinsn, + output reg [31:0] outop0, outop1, outop2 ); reg mult_start; @@ -69,6 +70,9 @@ module Execute( write_data <= next_write_data; outpc <= pc; outinsn <= insn; + outop0 <= op0; + outop1 <= op1; + outop2 <= op2; end end diff --git a/Memory.v b/Memory.v index 2378177..e10a2e7 100644 --- a/Memory.v +++ b/Memory.v @@ -37,11 +37,11 @@ module Memory( output reg [31:0] out_write_data = 32'hxxxxxxxx ); - reg [31:0] addr, raddr, next_regdata; - reg [3:0] next_regsel; - reg next_writeback, next_notdone, next_inc_next; + reg [31:0] addr, raddr; + reg next_notdone, next_inc_next; reg [31:0] align_s1, align_s2, align_rddata; - + + wire next_outbubble; wire next_write_reg; wire [3:0] next_write_num; wire [31:0] next_write_data; @@ -55,10 +55,10 @@ module Memory( begin outpc <= pc; outinsn <= insn; - outbubble <= rw_wait; - out_write_reg <= next_writeback; - out_write_num <= next_regsel; - out_write_data <= next_regdata; + outbubble <= next_outbubble; + out_write_reg <= next_write_reg; + out_write_num <= next_write_num; + out_write_data <= next_write_data; notdone <= next_notdone; inc_next <= next_inc_next; regs <= next_regs; @@ -78,12 +78,14 @@ module Memory( next_write_num = write_num; next_write_data = write_data; next_inc_next = 1'b0; + next_outbubble = inbubble; outstall = 1'b0; casez(insn) `DECODE_LDRSTR_UNDEFINED: begin end `DECODE_LDRSTR: begin if (!inbubble) begin + next_outbubble = rw_wait; outstall = rw_wait | notdone; addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ diff --git a/system.v b/system.v index da9d701..a0c35d6 100644 --- a/system.v +++ b/system.v @@ -46,28 +46,38 @@ module System(input clk); wire dcache_rw_wait; wire [31:0] dcache_wr_data, dcache_rd_data; - wire stall_cause_issue; - wire stall_cause_execute; - wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr; wire decode_out_carry; - wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2; - wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr; + + wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3; + wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr; + wire execute_out_write_reg; wire [3:0] execute_out_write_num; wire [31:0] execute_out_write_data; + wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2; wire [31:0] jmppc; wire jmp; + wire memory_out_write_reg; + wire [3:0] memory_out_write_num; + wire [31:0] memory_out_write_data; + + wire stall_cause_issue; + wire stall_cause_execute; + wire stall_cause_memory; wire bubble_out_fetch; wire bubble_out_issue; wire bubble_out_execute; + wire bubble_out_memory; wire [31:0] insn_out_fetch; wire [31:0] insn_out_issue; wire [31:0] insn_out_execute; + wire [31:0] insn_out_memory; wire [31:0] pc_out_fetch; wire [31:0] pc_out_issue; wire [31:0] pc_out_execute; + wire [31:0] pc_out_memory; wire execute_out_backflush; @@ -118,8 +128,8 @@ module System(input clk); RegFile regfile( .clk(clk), - .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), - .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), + .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_2(regfile_read_3), + .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_2(regfile_rdata_3), .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */)); Decode decode( @@ -132,7 +142,7 @@ module System(input clk); Execute execute( .clk(clk), .Nrst(1'b0), - .stall(1'b0 /* XXX */), .flush(1'b0), + .stall(stall_cause_memory), .flush(1'b0), .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue), .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2), .carry(decode_out_carry), @@ -140,8 +150,21 @@ module System(input clk); .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data), .jmp(jmp), .jmppc(jmppc), - .outpc(pc_out_execute), .outinsn(insn_out_execute)); + .outpc(pc_out_execute), .outinsn(insn_out_execute), + .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2)); assign execute_out_backflush = jmp; + + Memory memory( + .clk(clk), .Nrst(1'b0), + /* stall? flush? */ + .st_read(regfile_read_3), .st_data(regfile_rdata_3), + .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute), + .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2), + .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data), + .outstall(stall_cause_memory), .outbubble(bubble_out_memory), + .outpc(pc_out_memory), .outinsn(insn_out_memory), + .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), + .out_write_data(memory_out_write_data)); reg [31:0] clockno = 0; always @(posedge clk) @@ -152,5 +175,6 @@ module System(input clk); $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue); $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry); $display("%3d: EXEC: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp, jmppc); + $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num); end endmodule