From: Joshua Wise Date: Fri, 26 Dec 2008 13:31:14 +0000 (-0500) Subject: Merge nyus:/storage/git/firearm X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/960947a70a85ad40fe2569500806552d11f1e02d?hp=260493397ff323c936b295ec96d1e06710ece653 Merge nyus:/storage/git/firearm --- diff --git a/BlockRAM.v b/BlockRAM.v index 85f8659..1731c30 100644 --- a/BlockRAM.v +++ b/BlockRAM.v @@ -14,27 +14,30 @@ module BlockRAM( */ wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000; /* verilator lint_off WIDTH */ - wire [13:2] ramaddr = bus_addr & 32'h3FFC; /* mask off lower two bits + wire [13:0] ramaddr = bus_addr & 32'h3FFC; /* mask off lower two bits * for word alignment */ /* verilator lint_on WIDTH */ - reg [31:0] data [0:(16384 / 4 - 1)]; + reg [31:0] data [(16384 / 4 - 1):0]; - reg [31:0] temprdata; - reg [13:2] lastread; + reg [31:0] temprdata = 0; + reg [13:0] lastread = 14'h3FFF; assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0; assign bus_ready = decode && (bus_wr || (bus_rd && (lastread == ramaddr))); + initial + $readmemh("ram.hex", data); + always @(posedge clk) begin if (bus_wr && decode) - data[ramaddr] <= bus_wdata; + data[ramaddr[13:2]] <= bus_wdata; /* This is not allowed to be conditional -- stupid Xilinx * blockram. */ - temprdata <= data[ramaddr]; + temprdata <= data[ramaddr[13:2]]; lastread <= ramaddr; end endmodule diff --git a/Fetch.v b/Fetch.v index 0a18b31..3b6d9c5 100644 --- a/Fetch.v +++ b/Fetch.v @@ -10,32 +10,39 @@ module Fetch( input stall, input jmp, input [31:0] jmppc, - output wire bubble, - output wire [31:0] insn, - output reg [31:0] pc); + output reg bubble = 1, + output reg [31:0] insn = 0, + output reg [31:0] pc = 0); reg [31:0] prevpc; + reg [31:0] nextpc; initial prevpc = 32'hFFFFFFFC; /* ugh... the first pc we request will be this +4 */ always @(negedge Nrst) prevpc <= 32'hFFFFFFFC; - - always @(*) + + always @(*) if (!Nrst) - pc = 32'hFFFFFFFC; + nextpc = 32'hFFFFFFFC; else if (stall) /* don't change any internal state */ - pc = prevpc; + nextpc = prevpc; else if (jmp) - pc = jmppc; + nextpc = jmppc; else - pc = prevpc + 32'h4; + nextpc = prevpc + 32'h4; - assign bubble = stall | rd_wait; assign rd_addr = pc; assign rd_req = !stall; - assign insn = rd_data; always @(posedge clk) + begin if (!rd_wait || !Nrst) - prevpc <= pc; + prevpc <= nextpc; + if (!stall) + begin + bubble <= rd_wait; + insn <= rd_data; + pc <= nextpc; + end + end endmodule diff --git a/ICache.v b/ICache.v index 3a9f144..43f6028 100644 --- a/ICache.v +++ b/ICache.v @@ -10,7 +10,7 @@ module ICache( output reg [31:0] rd_data, /* bus interface */ - output reg bus_req, + output wire bus_req, input bus_ack, output reg [31:0] bus_addr, input [31:0] bus_rdata, @@ -35,7 +35,10 @@ module ICache( reg [4:0] i; initial for (i = 0; i < 16; i = i + 1) + begin cache_valid[i[3:0]] = 0; + cache_tags[i[3:0]] = 0; + end wire [5:0] rd_didx = rd_addr[5:0]; wire [3:0] rd_didx_word = rd_didx[5:2]; diff --git a/Issue.v b/Issue.v index a745656..03707d9 100644 --- a/Issue.v +++ b/Issue.v @@ -2,7 +2,7 @@ module Issue( input clk, - input Nrst, + input Nrst, /* XXX not used yet */ input stall, /* pipeline control */ input flush, @@ -12,10 +12,10 @@ module Issue( input [31:0] inpc, input [31:0] cpsr, - output reg outstall, /* stage outputs */ - output reg outbubble, - output reg [31:0] outpc, - output reg [31:0] outinsn + output reg outstall = 0, /* stage outputs */ + output reg outbubble = 1, + output reg [31:0] outpc = 0, + output reg [31:0] outinsn = 0 /* XXX other? */ ); @@ -264,26 +264,32 @@ module Issue( reg waiting_regs; wire waiting = waiting_cpsr | waiting_regs; + initial + begin + cpsr_inflight[0] = 0; + cpsr_inflight[1] = 0; + regs_inflight[0] = 0; + regs_inflight[1] = 0; + end + always @(*) begin waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); + + outstall = waiting && !inbubble; /* Happens in an always @*, because it is an exception. */ end /* Actually do the issue. */ - always @(*) - outstall = waiting; - always @(posedge clk) begin cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */ - cpsr_inflight[1] <= (waiting | inbubble) ? 0 : def_cpsr; + cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr; regs_inflight[0] <= regs_inflight[1]; - regs_inflight[1] <= (waiting | inbubble) ? 0 : def_regs; + regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs; outbubble <= inbubble | waiting | !condition_met; outpc <= inpc; outinsn <= insn; end - endmodule diff --git a/system.v b/system.v index 0c25de3..afd7a17 100644 --- a/system.v +++ b/system.v @@ -32,6 +32,22 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp wire icache_rd_req; wire icache_rd_wait; wire [31:0] icache_rd_data; + + wire stall_cause_issue; + + wire stall_in_fetch = stall_cause_issue; + wire stall_in_issue = 0; + + wire bubble_out_fetch; + wire bubble_out_issue; + wire [31:0] insn_out_fetch; + wire [31:0] insn_out_issue; + wire [31:0] pc_out_fetch; + wire [31:0] pc_out_issue; + + assign bubbleshield = bubble_out_issue; + assign insn = insn_out_issue; + assign pc = pc_out_issue; BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack)); @@ -56,7 +72,23 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp .Nrst(1 /* XXX */), .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), - .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */), - .bubble(bubbleshield), .insn(insn), .pc(pc)); - + .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */), + .bubble(bubble_out_fetch), .insn(insn_out_fetch), + .pc(pc_out_fetch)); + + Issue issue( + .clk(clk), + .Nrst(1 /* XXX */), + .stall(stall_in_issue), .flush(0 /* XXX */), + .inbubble(bubble_out_fetch), .insn(insn_out_fetch), + .inpc(pc_out_fetch), .cpsr(0 /* XXX */), + .outstall(stall_cause_issue), .outbubble(bubble_out_issue), + .outpc(pc_out_issue), .outinsn(insn_out_issue)); + + always @(posedge clk) + begin + $display("Clock-time dump:"); + $display("Fetch stage: Bubble output: %d, Instruction: %08x, PC: %08x", bubble_out_fetch, insn_out_fetch, pc_out_fetch); + $display("Issue stage: Stall output: %d, Bubble output: %d, Instruction: %08x, PC: %08x", stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue); + end endmodule