From: Joshua Wise <joshua@nyus.joshuawise.com>
Date: Mon, 22 Dec 2008 07:24:21 +0000 (-0500)
Subject: Wire the fetch unit into the top module
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/5d9760a4dd32206c26c9f20fb995d29160bcbf71?hp=bd0731755c59cae2ae02842e17fc77f4668301bc

Wire the fetch unit into the top module
---

diff --git a/system.v b/system.v
index ebf0882..1035489 100644
--- a/system.v
+++ b/system.v
@@ -1,6 +1,6 @@
 `define BUS_ICACHE 0
 
-module System(input clk);
+module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
 	wire [7:0] bus_req;
 	wire [7:0] bus_ack;
 	wire [31:0] bus_addr;
@@ -25,12 +25,19 @@ module System(input clk);
 	assign bus_rd = bus_rd_icache;
 	assign bus_wr = bus_wr_icache;
 	assign bus_ready = bus_ready_blockram;
+	
+	wire [31:0] icache_rd_addr;
+	wire icache_rd_req;
+	wire icache_rd_wait;
+	wire [31:0] icache_rd_data;
 
 	BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
 	ICache icache(
 		.clk(clk),
-		.rd_addr(), .rd_req(), .rd_wait(), .rd_data(),
+		/* XXX reset? */
+		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
+		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
 		.bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
 		.bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
 		.bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
@@ -42,4 +49,12 @@ module System(input clk);
 		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
 		.bus_ready(bus_ready_blockram));
 
+	Fetch fetch(
+		.clk(clk),
+		.Nrst(1 /* XXX */),
+		.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
+		.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
+		.stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
+		.bubble(bubbleshield), .insn(insn), .pc(pc));
+
 endmodule