From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 14 Jan 2009 07:14:19 +0000 (-0500)
Subject: ICache and DCache: Do not accept fill data if the bus_ready is actually intended... 
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/52fd78ff62b919c5dd5e59af2550e4ff733816a1

ICache and DCache: Do not accept fill data if the bus_ready is actually intended for someone *else*.
---

diff --git a/DCache.v b/DCache.v
index a3484a7..edfcde1 100644
--- a/DCache.v
+++ b/DCache.v
@@ -79,7 +79,7 @@ module DCache(
 		if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
 		else if (rd_req && !cache_hit) begin
-			if (bus_ready) begin	/* Started the fill, and we have data. */
+			if (bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
 				cache_data[idx][cache_fill_pos] <= bus_rdata;
 				cache_fill_pos <= cache_fill_pos + 1;
 				if (cache_fill_pos == 15) begin	/* Done? */
diff --git a/ICache.v b/ICache.v
index 8106259..b9e4eff 100644
--- a/ICache.v
+++ b/ICache.v
@@ -70,7 +70,7 @@ module ICache(
 		if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
 		else if (rd_req && !cache_hit) begin
-			if (bus_ready) begin	/* Started the fill, and we have data. */
+			if (bus_ack && bus_ready) begin	/* Started the fill, and we have data. */
 				$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
 				cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
 				cache_fill_pos <= cache_fill_pos + 1;