From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Wed, 7 Jan 2009 09:25:50 +0000 (-0500)
Subject: Memory: Add CDP and MRC/MCR.
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/43e4332c59b61779d656eb95f058b36af031cbcb

Memory: Add CDP and MRC/MCR.
---

diff --git a/Memory.v b/Memory.v
index 658e7d2..2885add 100644
--- a/Memory.v
+++ b/Memory.v
@@ -20,6 +20,9 @@ module Memory(
 	output reg cp_req,
 	input cp_ack,
 	input cp_busy,
+	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
+	input [31:0] cp_read,
+	output reg [31:0] cp_write,
 	
 	/* stage inputs */
 	input inbubble,
@@ -101,6 +104,8 @@ module Memory(
 		next_regs = 16'b0;
 		next_started = started;
 		cp_req = 1'b0;
+		cp_rnw = 1'bx;
+		cp_write = 32'hxxxxxxxx;
 		offset = prev_offset;
 		next_outcpsr = started ? out_cpsr : cpsr;
 
@@ -257,6 +262,38 @@ module Memory(
 				busaddr = {raddr[31:2], 2'b0};
 			end
 		end
+		`DECODE_LDCSTC: begin
+			$display("WARNING: Unimplemented LDCSTC");
+		end
+		`DECODE_CDP: begin
+			cp_req = 1;
+			if (cp_busy) begin
+				outstall = 1;
+				next_outbubble = 1;
+			end
+			if (!cp_ack) begin
+				/* XXX undefined instruction trap */
+				$display("WARNING: Possible CDP undefined instruction");
+			end
+		end
+		`DECODE_MRCMCR: begin
+			cp_req = 1;
+			cp_rnw = insn[20] /* L */;
+			if (insn[20] == 0 /* store to coprocessor */)
+				cp_write = op0;
+			else begin
+				next_write_reg = 1'b1;
+				next_write_num = insn[15:12];
+				next_write_data = cp_read;
+			end
+			if (cp_busy) begin
+				outstall = 1;
+				next_outbubble = 1;
+			end
+			if (!cp_ack) begin
+				$display("WARNING: Possible MRCMCR undefined instruction");
+			end
+		end
 		default: begin end
 		endcase
 	end
diff --git a/system.v b/system.v
index fdefc54..b8fc48e 100644
--- a/system.v
+++ b/system.v
@@ -63,6 +63,13 @@ module System(input clk);
 	wire [3:0] memory_out_write_num;
 	wire [31:0] memory_out_write_data;
 	
+	wire cp_req;
+	wire cp_ack = 0;
+	wire cp_busy = 0;
+	wire cp_rnw;
+	wire [31:0] cp_read = 0;
+	wire [31:0] cp_write;
+	
 	wire stall_cause_issue;
 	wire stall_cause_execute;
 	wire stall_cause_memory;
@@ -166,7 +173,8 @@ module System(input clk);
 		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
 		.outpc(pc_out_memory), .outinsn(insn_out_memory),
 		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
-		.out_write_data(memory_out_write_data));
+		.out_write_data(memory_out_write_data),
+		.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write));
 
 	reg [31:0] clockno = 0;
 	always @(posedge clk)