From: Joshua Wise <joshua@nyus.joshuawise.com>
Date: Mon, 22 Dec 2008 05:03:53 +0000 (-0500)
Subject: Add the blockram.
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/2f8f0594f45ef78f4f3c5c0c209c889c931bc863?hp=ee4068391a94ca33bcec919274ef17496c0a7d6b;ds=sidebyside

Add the blockram.
---

diff --git a/blockram.v b/blockram.v
new file mode 100644
index 0000000..fd36875
--- /dev/null
+++ b/blockram.v
@@ -0,0 +1,38 @@
+module BlockRAM(
+	input clk,
+	input [31:0] bus_addr,
+	output wire [31:0] bus_rdata,
+	input [31:0] bus_wdata,
+	input bus_rd,
+	input bus_wr,
+	output wire bus_ready
+	);
+	
+	/* This module is mapped in physical memory from 0x00000000 to
+	 * 0x00004000.  rdata and ready must be driven to zero if the
+	 * address is not within the range of this module.
+	 */
+	wire decode = (addr & ~32'h00003FFF) == 32'h00004000;
+	wire [13:2] ramaddr = addr & 14'h3FFC;	/* mask off lower two bits
+						 * for word alignment */
+	
+	reg [31:0] data [0:(16384 / 4 - 1)];
+	
+	reg [31:0] temprdata;
+	reg [13:2] lastread;
+	assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
+	
+	assign bus_ready = decode &&
+		(bus_wr || (bus_rd && (lastread == ramaddr)));
+	
+	always @(posedge clk)
+	begin
+		if (bus_wr && decode)
+			data[ramaddr] <= bus_wdata;
+		
+		/* This is not allowed to be conditional -- stupid Xilinx
+		 * blockram. */
+		temprdata <= data[ramaddr];
+		lastread <= ramaddr;
+	end
+endmodule