From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 24 Jan 2009 10:37:43 +0000 (-0500)
Subject: DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on... 
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/2b5c79c05898ff20b0c04cd78bccb2580f6c8331?hp=fd003c7a793fb17fb6dc7ba52873b883b28a578b;ds=sidebyside

DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on Xilinx.
---

diff --git a/BlockRAM.v b/BlockRAM.v
index e0eceeb..091c749 100644
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -31,11 +31,11 @@ module BlockRAM(
 	always @(posedge clk)
 	begin
 		if (bus_wr && decode)
-			data[ramaddr[13:2]] = bus_wdata;
+			data[ramaddr[13:2]] <= bus_wdata;
 		
 		/* This is not allowed to be conditional -- stupid Xilinx
 		 * blockram. */
-		temprdata <= data[ramaddr[13:2]];
+		temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
 		lastread <= ramaddr;
 	end
 endmodule
diff --git a/DCache.v b/DCache.v
index f4dff5a..aec6ae6 100644
--- a/DCache.v
+++ b/DCache.v
@@ -29,7 +29,7 @@ module DCache(
 	
 	reg cache_valid [15:0];
 	reg [21:0] cache_tags [15:0];
-	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	reg [31:0] cache_data [255:0 /* {line,word} */];
 
 	integer i;	
 	initial
@@ -48,7 +48,7 @@ module DCache(
 	
 	wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
 	
-	wire [31:0] curdata = cache_data[idx][didx_word];
+	wire [31:0] curdata = cache_data[{idx,didx_word}];
 	always @(*) begin
 		rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
 		rd_data = curdata;
@@ -79,18 +79,18 @@ module DCache(
 		prev_addr <= {addr[31:6], 6'b0};
 		if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
-		else if (rd_req && !cache_hit) begin
-			if (bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
-				$display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
-				cache_data[idx][cache_fill_pos] <= bus_rdata;
-				cache_fill_pos <= cache_fill_pos + 1;
-				if (cache_fill_pos == 15) begin	/* Done? */
-					cache_tags[idx] <= tag;
-					cache_valid[idx] <= 1;
-				end else
-					cache_valid[idx] <= 0;
-			end
-		end else if (wr_req && cache_hit)
-			cache_data[idx][addr[5:2]] <= wr_data;
+		else if (rd_req && !cache_hit && bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
+			$display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
+			cache_fill_pos <= cache_fill_pos + 1;
+			if (cache_fill_pos == 15) begin	/* Done? */
+				cache_tags[idx] <= tag;
+				cache_valid[idx] <= 1;
+			end else
+				cache_valid[idx] <= 0;
+		end
+		
+		/* Split this out because XST is kind of silly about this sort of thing. */
+		if ((rd_req && !cache_hit && bus_ready && bus_ack) || (wr_req && cache_hit))
+			cache_data[wr_req ? {idx,addr[5:2]} : {idx,cache_fill_pos}] <= wr_req ? wr_data : bus_rdata;
 	end
 endmodule
diff --git a/ICache.v b/ICache.v
index e6754b7..8b9eac3 100644
--- a/ICache.v
+++ b/ICache.v
@@ -30,7 +30,7 @@ module ICache(
 	
 	reg cache_valid [15:0];
 	reg [21:0] cache_tags [15:0];
-	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	reg [31:0] cache_data [255:0 /* {line, word} */];	//synthesis attribute ram_style of cache_data is distributed
 	
 	integer i;
 	initial
@@ -48,12 +48,6 @@ module ICache(
 	reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
 	
 	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
-
-	wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
-	always @(*) begin
-		rd_wait = rd_req && !cache_hit;
-		rd_data = curdata;
-	end
 	
 	reg [3:0] cache_fill_pos = 0;
 	assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
@@ -65,23 +59,27 @@ module ICache(
 			bus_addr = 0;
 			bus_rd = 0;
 		end
+
+	wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}];
+	always @(*) begin
+		rd_wait = rd_req && !cache_hit;
+		rd_data = curdata;
+	end
 	
 	always @(posedge clk) begin
 		prev_rd_addr <= {rd_addr[31:6], 6'b0};
 		if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
-		else if (rd_req && !cache_hit) begin
-			if (bus_ack && bus_ready) begin	/* Started the fill, and we have data. */
-				$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
-				cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
-				cache_fill_pos <= cache_fill_pos + 1;
-				if (cache_fill_pos == 15) begin	/* Done? */
-					cache_tags[rd_idx] <= rd_tag;
-					cache_valid[rd_idx] <= 1;
-					$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
-				end else
-					cache_valid[rd_idx] <= 0;
-			end
+		else if (rd_req && !cache_hit && bus_ack && bus_ready) begin
+			$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+			cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata;
+			cache_fill_pos <= cache_fill_pos + 1;
+			if (cache_fill_pos == 15) begin	/* Done? */
+				cache_tags[rd_idx] <= rd_tag;
+				cache_valid[rd_idx] <= 1;
+				$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
+			end else
+				cache_valid[rd_idx] <= 0;
 		end
 	end
 endmodule
diff --git a/ram.hex b/ram.hex
index 96b3cdf..6d0fcf5 120000
--- a/ram.hex
+++ b/ram.hex
@@ -1 +1 @@
-tests/u-boot.hex
\ No newline at end of file
+tests/testbench.hex
\ No newline at end of file