From: Joshua Wise Date: Fri, 12 Mar 2010 15:09:29 +0000 (-0500) Subject: Add support for CellularRAM on Nexys2. X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/1e7ff543e49341fedea742d7b8b674111d852748?ds=inline Add support for CellularRAM on Nexys2. --- diff --git a/BigBlockRAM.v b/BigBlockRAM.v index 7e6ea99..7b8275a 100644 --- a/BigBlockRAM.v +++ b/BigBlockRAM.v @@ -10,9 +10,10 @@ module BigBlockRAM( /* This module is mapped in physical memory from 0x00000000 to * 0x00800000. rdata and ready must be driven to zero if the - * address is not within the range of this module. + * address is not within the range of this module. There also + * exists a shadow up at 0x80000000. */ - wire decode = bus_addr[31:23] == 9'b0; + wire decode = bus_addr[30:23] == 8'b0; wire [22:0] ramaddr = {bus_addr[22:2], 2'b0}; /* mask off lower two bits * for word alignment */ diff --git a/CellularRAM.v b/CellularRAM.v new file mode 100644 index 0000000..81622cd --- /dev/null +++ b/CellularRAM.v @@ -0,0 +1,50 @@ +module CellularRAM( + input clk, + input [31:0] bus_addr, + output wire [31:0] bus_rdata, + input [31:0] bus_wdata, + input bus_rd, + input bus_wr, + output wire bus_ready, + + output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, + inout wire [15:0] cr_DQ, + output wire [22:0] cr_A, + output wire st_nCE + ); + + /* This module is mapped in physical memory from 0x80000000 to + * 0x80FFFFFF. rdata and ready must be driven to zero if the + * address is not within the range of this module. + */ + wire decode = bus_addr[31:24] == 8'h80; + assign cr_A = bus_addr[23:1]; + reg [22:0] cr_A_1a = 23'h7FFFFF; + reg [22:0] cr_A_2a = 23'h7FFFFF; + wire active = (decode && (bus_rd || bus_wr)); + reg active_1a = 0; + reg active_2a = 0; + + always @(posedge clk) + begin + cr_A_1a <= cr_A; + cr_A_2a <= cr_A_1a; + active_1a <= active; + active_2a <= active_1a; + end + + assign bus_rdata = (bus_rd && decode) ? {16'h0000, cr_DQ} : 32'h0; + assign cr_DQ = (bus_wr && decode) ? bus_wdata : 16'hzzzz; + + assign bus_ready = active && active_1a && active_2a && (cr_A_1a == cr_A) && (cr_A_2a == cr_A); + + assign st_nCE = 0; + assign cr_nADV = ~decode; + assign cr_nCE = 0; + assign cr_nOE = ~bus_rd; + assign cr_nWE = ~bus_wr; + assign cr_CRE = 0; + assign cr_nLB = 0; + assign cr_nUB = 0; + assign cr_CLK = 0; +endmodule diff --git a/Makefile b/Makefile index 2c4bf60..7649562 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -VLOGS = ARM_Constants.v BigBlockRAM.v BlockRAM.v BusArbiter.v DCache.v Decode.v Execute.v Fetch.v ICache.v Issue.v Memory.v Minishift.v RegFile.v Terminal.v Writeback.v system.v +VLOGS = ARM_Constants.v BigBlockRAM.v BlockRAM.v BusArbiter.v DCache.v Decode.v Execute.v Fetch.v ICache.v Issue.v Memory.v Minishift.v RegFile.v Terminal.v Writeback.v system.v CellularRAM.v all: Vsystem diff --git a/ram.hex b/ram.hex index aa3a6ed..5d115b1 120000 --- a/ram.hex +++ b/ram.hex @@ -1 +1 @@ -tests/testbench.pad.hex \ No newline at end of file +tests/ram.hex \ No newline at end of file diff --git a/system.v b/system.v index 8205a15..97880c9 100644 --- a/system.v +++ b/system.v @@ -6,7 +6,12 @@ module System(input clk, input rst `else , output wire [8:0] sys_odata, input [8:0] sys_idata, - output wire sys_tookdata + output wire sys_tookdata, + + output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, + inout wire [15:0] cr_DQ, + output wire [22:0] cr_A, + output wire st_nCE `endif ); @@ -34,15 +39,15 @@ module System(input clk, input rst wire bus_rd_dcache; wire bus_wr_dcache; - wire [31:0] bus_rdata_blockram; - wire bus_ready_blockram; + wire [31:0] bus_rdata_blockram, bus_rdata_cellularram; + wire bus_ready_blockram, bus_ready_cellularram; assign bus_addr = bus_addr_icache | bus_addr_dcache; - assign bus_rdata = bus_rdata_blockram; + assign bus_rdata = bus_rdata_blockram | bus_rdata_cellularram; assign bus_wdata = bus_wdata_icache | bus_wdata_dcache; assign bus_rd = bus_rd_icache | bus_rd_dcache; assign bus_wr = bus_wr_icache | bus_wr_dcache; - assign bus_ready = bus_ready_blockram; + assign bus_ready = bus_ready_blockram | bus_ready_cellularram; wire [31:0] icache_rd_addr; wire icache_rd_req; @@ -239,6 +244,40 @@ module System(input clk, input rst .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr), .bus_ready(bus_ready_blockram)); +`ifdef verilator + assign bus_rdata_cellularram = 32'h00000000; + assign bus_ready_cellularram = 0; +`else + /* CellularRAM AUTO_TEMPLATE ( + .bus_rdata(bus_rdata_cellularram), + .bus_ready(bus_ready_cellularram), + ); + */ + CellularRAM cellularram( + /*AUTOINST*/ + // Outputs + .bus_rdata (bus_rdata_cellularram), // Templated + .bus_ready (bus_ready_cellularram), // Templated + .cr_nADV (cr_nADV), + .cr_nCE (cr_nCE), + .cr_nOE (cr_nOE), + .cr_nWE (cr_nWE), + .cr_CRE (cr_CRE), + .cr_nLB (cr_nLB), + .cr_nUB (cr_nUB), + .cr_CLK (cr_CLK), + .cr_A (cr_A[22:0]), + .st_nCE (st_nCE), + // Inouts + .cr_DQ (cr_DQ[15:0]), + // Inputs + .clk (clk), + .bus_addr (bus_addr[31:0]), + .bus_wdata (bus_wdata[31:0]), + .bus_rd (bus_rd), + .bus_wr (bus_wr)); +`endif + /* Fetch AUTO_TEMPLATE ( .jmp_0a(jmp), .jmppc_0a(jmppc), diff --git a/tests/Makefile b/tests/Makefile index 471a83e..774222d 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -1,6 +1,6 @@ CFLAGS=-mno-thumb-interwork -march=armv4 -all: costas.hex testbench.hex +all: costas.hex testbench.pad.hex testbench.hex %.o: %.c arm-elf-gcc $(CFLAGS) -c -o $@ $< diff --git a/tests/testbench.c b/tests/testbench.c index e708df6..f078ecd 100644 --- a/tests/testbench.c +++ b/tests/testbench.c @@ -102,10 +102,30 @@ void ldm_tester() puts("PASS\n"); } +void cellularram() +{ + volatile int *p = 0x80010000; + + puts("[writing] "); + p[0] = 0x12345678; + p[1] = 0x87654321; + p[2] = 0xAAAA5555; + p[3] = 0x5555AAAA; + puts("[cache flush] "); + p[0x1000] = 0x00000000; + puts("[reading: "); + puthex(p[0]); + puthex(p[1]); + puthex(p[2]); + puthex(p[3]); + puts("]\n"); +} + struct tests tlist[] = { {"ldm pc/mul", ldm_tester}, {"fact", facttest}, {"j4cbo", j4cbo}, + {"cellularram", cellularram}, {"ack", acktest}, {"miniblarg", testmain}, {"corecurse", corecurse}, diff --git a/tests/testbench.hex b/tests/testbench.hex index 1335254..37a227a 100644 Binary files a/tests/testbench.hex and b/tests/testbench.hex differ diff --git a/tests/testbench.pad.hex b/tests/testbench.pad.hex index eecc6d5..bf3d259 100644 Binary files a/tests/testbench.pad.hex and b/tests/testbench.pad.hex differ diff --git a/xst/Console.nexys2.v b/xst/Console.nexys2.v new file mode 100644 index 0000000..bf42439 --- /dev/null +++ b/xst/Console.nexys2.v @@ -0,0 +1,406 @@ +module MulDivDCM(input xtal, output clk); + parameter div = 5; + parameter mul = 2; + + wire CLKFX_BUF; + wire GND_BIT = 0; + BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), + .O(clk)); + DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), + .CLKIN(xtal), + .DSSEN(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKFX(CLKFX_BUF)); + defparam DCM_SP_INST.CLK_FEEDBACK = "NONE"; + defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_SP_INST.CLKFX_DIVIDE = div; + defparam DCM_SP_INST.CLKFX_MULTIPLY = mul; + defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; + defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_SP_INST.FACTORY_JF = 16'hC080; + defparam DCM_SP_INST.PHASE_SHIFT = 0; + defparam DCM_SP_INST.STARTUP_WAIT = "TRUE"; +endmodule + +module Console( + input xtal, + input rst, + output wire rstact, + output wire vs, hs, + output wire [2:0] r, g, + output wire [1:0] b, + input ps2c, ps2d, + output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, + inout wire [15:0] cr_DQ, + output wire [22:0] cr_A, + output wire st_nCE); + + wire pixclk, coreclk; + + wire [11:0] x, y; + wire border; + + assign coreclk = pixclk; + MulDivDCM dcm31_25(xtal, pixclk); + defparam dcm31_25.div = 4; + defparam dcm31_25.mul = 2; + + SyncGen sync(pixclk, vs, hs, x, y, border); + + wire [7:0] cschar; + wire [2:0] csrow; + wire [7:0] csdata; + + wire [10:0] vraddr; + wire [7:0] vrdata; + + wire [10:0] vwaddr; + wire [7:0] vwdata; + wire [7:0] serdata; + wire vwr, serwr; + wire [10:0] vscroll; + + wire odata; + + wire [6:0] vcursx; + wire [4:0] vcursy; + + reg [16:0] rsttimer = 17'h3FFFF; + always @(posedge coreclk) + if (rst) + rsttimer <= 17'h3FFFF; + else if (rsttimer) + rsttimer <= rsttimer - 1; + assign rstact = rsttimer != 17'h0; + + wire tookdata; + reg ps2_hasd = 0; + reg [7:0] ps2_d = 0; + wire sertxwr; + wire [7:0] sertxdata; + + CharSet cs(cschar, csrow, csdata); + VideoRAM vram(pixclk, vraddr + vscroll, vrdata, coreclk, vwaddr, vwdata, vwr); + VDisplay dpy(pixclk, x, y, vraddr, vrdata, cschar, csrow, csdata, vcursx, vcursy, odata); + RXState rxsm(coreclk, vwr, vwaddr, vwdata, vscroll, vcursx, vcursy, serwr, serdata); + PS2 ps2(coreclk, ps2c, ps2d, sertxwr, sertxdata); + System sys(.clk(coreclk), .rst(rstact), .sys_odata({serwr, serdata}), .sys_idata({ps2_hasd, ps2_d}), .sys_tookdata(tookdata), + .cr_nADV (cr_nADV), + .cr_nCE (cr_nCE), + .cr_nOE (cr_nOE), + .cr_nWE (cr_nWE), + .cr_CRE (cr_CRE), + .cr_nLB (cr_nLB), + .cr_nUB (cr_nUB), + .cr_CLK (cr_CLK), + .cr_A (cr_A), + .st_nCE (st_nCE), + .cr_DQ (cr_DQ)); + + always @(posedge coreclk) + if (sertxwr) + {ps2_hasd, ps2_d} <= {1'b1, sertxdata}; + else if (tookdata) + {ps2_hasd, ps2_d} <= {1'b0, 8'hxxxxxxxx}; + + wire [7:0] red, green, blue; + assign r = (odata ? 3'b111 : 0) | (x[8:7] ^ y[7:6]); + assign g = (odata ? 3'b111 : 0) | (x[7:6] ^ y[8:7]); + assign b = (odata ? 2'b11 : 0) | (x[8 ] ^ y[8 ]); +endmodule + +module SyncGen( + input pixclk, + output reg vs, hs, + output reg [11:0] x, y, + output reg border); + + parameter XRES = 640; + parameter XFPORCH = 16; + parameter XSYNC = 96; + parameter XBPORCH = 48; + + parameter YRES = 480; + parameter YFPORCH = 10; + parameter YSYNC = 2; + parameter YBPORCH = 29; + + always @(posedge pixclk) + begin + if (x >= (XRES + XFPORCH + XSYNC + XBPORCH)) + begin + if (y >= (YRES + YFPORCH + YSYNC + YBPORCH)) + y = 0; + else + y = y + 1; + x = 0; + end else + x = x + 1; + hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC)); + vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC)); + border <= (x > XRES) || (y > YRES); + end +endmodule + +module CharSet( + input [7:0] char, + input [2:0] row, + output wire [7:0] data); + + reg [7:0] rom [(256 * 8 - 1):0]; + + initial + $readmemb("ibmpc1.mem", rom); + + assign data = rom[{char, row}]; +endmodule + +module VideoRAM( + input pixclk, + input [10:0] raddr, + output reg [7:0] rdata, + input wclk, + input [10:0] waddr, + input [7:0] wdata, + input wr); + + reg [7:0] ram [2047 : 0]; + + always @(posedge pixclk) + rdata <= ram[raddr]; + + always @(posedge wclk) + if (wr) + ram[waddr] <= wdata; +endmodule + +module VDisplay( + input pixclk, + input [11:0] x, + input [11:0] y, + output wire [10:0] raddr, + input [7:0] rchar, + output wire [7:0] cschar, + output wire [2:0] csrow, + input [7:0] csdata, + input [6:0] cursx, + input [4:0] cursy, + output reg data); + + wire [7:0] col = x[11:3]; + wire [5:0] row = y[10:4]; + reg [7:0] ch; + reg [11:0] xdly; + + assign raddr = ({row,4'b0} + {row,6'b0} + {4'h0,col}); + assign cschar = rchar; + assign csrow = y[3:1]; + + reg [23:0] blinktime = 0; + + always @(posedge pixclk) blinktime <= blinktime + 1; + + wire curssel = (cursx == col) && (cursy == row) && blinktime[23]; + + always @(posedge pixclk) + xdly <= x; + + always @(posedge pixclk) + data = ((xdly < 80 * 8) && (y < 25 * 16)) ? (csdata[7 - xdly[2:0]] ^ curssel) : 0; +endmodule + +module RXState( + input clk25, + output reg vwr = 0, + output reg [10:0] vwaddr = 0, + output reg [7:0] vwdata = 0, + output reg [10:0] vscroll = 0, + output wire [6:0] vcursx, + output wire [4:0] vcursy, + input serwr, + input [7:0] serdata); + + parameter STATE_IDLE = 4'b0000; + parameter STATE_NEWLINE = 4'b0001; + parameter STATE_CLEAR = 4'b0010; + + reg [3:0] state = STATE_CLEAR; + + reg [6:0] x = 0; + reg [4:0] y = 0; + + assign vcursx = x; + assign vcursy = y; + + reg [10:0] clearstart = 0; + reg [10:0] clearend = 11'b11111111111; + + always @(posedge clk25) + case (state) + STATE_IDLE: if (serwr) begin + if (serdata == 8'h0A) begin + state <= STATE_NEWLINE; + x <= 0; + vwr <= 0; + end else if (serdata == 8'h0D) begin + x <= 0; + vwr <= 0; + end else if (serdata == 8'h0C) begin + clearstart <= 0; + clearend <= 11'b11111111111; + x <= 0; + y <= 0; + vscroll <= 0; + state <= STATE_CLEAR; + end else if (serdata == 8'h08) begin + if (x != 0) + x <= x - 1; + vwr <= 0; + end else begin + vwr <= 1; + vwaddr <= ({y,4'b0} + {y,6'b0} + {4'h0,x}) + vscroll; + vwdata <= serdata; + if (x == 79) begin + x <= 0; + state <= STATE_NEWLINE; + end else + x <= x + 1; + end + end + STATE_NEWLINE: + begin + vwr <= 0; + if (y == 24) begin + vscroll <= vscroll + 80; + clearstart <= (25 * 80) + vscroll; + clearend <= (26*80) + vscroll; + state <= STATE_CLEAR; + end else begin + y <= y + 1; + state <= STATE_IDLE; + end + end + STATE_CLEAR: + begin + vwr <= 1; + vwaddr <= clearstart; + vwdata <= 8'h20; + clearstart <= clearstart + 1; + if (clearstart == clearend) + state <= STATE_IDLE; + end + endcase +endmodule + +module PS2( + input pixclk, + input inclk, + input indata, + output reg wr, + output reg [7:0] data + ); + + reg [3:0] bitcount = 0; + reg [7:0] key = 0; + reg keyarrow = 0, keyup = 0, parity = 0; + + + /* Clock debouncing */ + reg lastinclk = 0; + reg [6:0] debounce = 0; + reg fixedclk = 0; + reg [11:0] resetcountdown = 0; + + reg [6:0] unshiftedrom [127:0]; initial $readmemh("scancodes.unshifted.hex", unshiftedrom); + reg [6:0] shiftedrom [127:0]; initial $readmemh("scancodes.shifted.hex", shiftedrom); + + reg mod_lshift = 0; + reg mod_rshift = 0; + reg mod_capslock = 0; + wire mod_shifted = (mod_lshift | mod_rshift) ^ mod_capslock; + + reg nd = 0; + reg lastnd = 0; + + always @(posedge pixclk) begin + if (inclk != lastinclk) begin + lastinclk <= inclk; + debounce <= 1; + resetcountdown <= 12'b111111111111; + end else if (debounce == 0) begin + fixedclk <= inclk; + resetcountdown <= resetcountdown - 1; + end else + debounce <= debounce + 1; + + if (nd ^ lastnd) begin + lastnd <= nd; + wr <= 1; + end else + wr <= 0; + end + + always @(negedge fixedclk) begin + if (resetcountdown == 0) + bitcount <= 0; + else if (bitcount == 10) begin + bitcount <= 0; + if(parity != (^ key)) begin + if(keyarrow) begin + casex(key) + 8'hF0: keyup <= 1; + 8'hxx: keyarrow <= 0; + endcase + end + else begin + if(keyup) begin + keyup <= 0; + keyarrow <= 0; + casex (key) + 8'h12: mod_lshift <= 0; + 8'h59: mod_rshift <= 0; + endcase + // handle this? I don't fucking know + end + else begin + casex(key) + 8'hE0: keyarrow <= 1; // handle these? I don't fucking know + 8'hF0: keyup <= 1; + 8'h12: mod_lshift <= 1; + 8'h59: mod_rshift <= 1; + 8'h14: mod_capslock <= ~mod_capslock; + 8'b0xxxxxxx: begin nd <= ~nd; data <= mod_shifted ? shiftedrom[key] : unshiftedrom[key]; end + 8'b1xxxxxxx: begin /* AAAAAAASSSSSSSS */ end + endcase + end + end + end + else begin + keyarrow <= 0; + keyup <= 0; + end + end else + bitcount <= bitcount + 1; + + case(bitcount) + 1: key[0] <= indata; + 2: key[1] <= indata; + 3: key[2] <= indata; + 4: key[3] <= indata; + 5: key[4] <= indata; + 6: key[5] <= indata; + 7: key[6] <= indata; + 8: key[7] <= indata; + 9: parity <= indata; + endcase + end + +endmodule diff --git a/xst/FireARM.ucf b/xst/FireARM.ucf index d26adb9..e0c4f58 100644 --- a/xst/FireARM.ucf +++ b/xst/FireARM.ucf @@ -1,33 +1,77 @@ -NET "xtal" LOC="ah15" | CLOCK_DEDICATED_ROUTE = FALSE | TNM_NET = xtal; -TIMESPEC "TS_xtal"=PERIOD "xtal" 100 MHz HIGH 50%; - -NET "dvi_d<11>" LOC="AN14" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<10>" LOC="AP14" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<9>" LOC="AB10" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<8>" LOC="AA10" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<7>" LOC="AN13" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<6>" LOC="AM13" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<5>" LOC="AA8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<4>" LOC="AA9" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<3>" LOC="AP12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<2>" LOC="AN12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<1>" LOC="AC8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_d<0>" LOC="AB8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_xclk_p" LOC="AL11" | TNM="dvi_c" | IOSTANDARD=LVDCI_33; -NET "dvi_xclk_n" LOC="AL10" | TNM="dvi_c" | IOSTANDARD=LVDCI_33; -NET "dvi_hs" LOC="AM12" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_vs" LOC="AM11" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_de" LOC="AE8" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; -NET "dvi_reset_b" LOC="AK6" | TNM="dvi_d" | IOSTANDARD=LVDCI_33; - -NET "dvi_scl" LOC="u27" | SLEW=fast | PULLUP; -NET "dvi_sda" LOC="t29" | SLEW=fast | PULLUP; - -TIMESPEC "TS_dvi_setup" = FROM dvi_c TO dvi_d 500 ps; -TIMESPEC "TS_dvi_hold" = FROM dvi_d TO dvi_c 500 ps; - -NET "rst" LOC="E9"; -NET "rstact" LOC="F6"; - -NET "ps2c" LOC="T26" | CLOCK_DEDICATED_ROUTE = FALSE; -NET "ps2d" LOC="T25"; +NET "xtal" LOC="B8" | CLOCK_DEDICATED_ROUTE = FALSE | TNM_NET = xtal; +TIMESPEC "TS_xtal"=PERIOD "xtal" 50 MHz HIGH 50%; +//NET "coreclk" TNM = coreclk; + +//TIMESPEC TSctl = FROM coreclk TO CR_CTL 5ns; +//TIMESPEC TSdatao = FROM coreclk TO CR_DATA 5ns; +//TIMESPEC TSdatai = FROM CR_DATA TO coreclk 5ns; +//TIMESPEC TSaddr = FROM coreclk TO CR_ADDR 5ns; + +NET "cr_nADV" LOC="J4" | SLEW="fast" | TNM = CR_CTL; +NET "cr_nCE" LOC="R6" | SLEW="fast" | TNM = CR_CTL; +NET "cr_nOE" LOC="T2" | SLEW="fast" | TNM = CR_CTL; +NET "cr_nWE" LOC="N7" | SLEW="fast" | TNM = CR_CTL; +NET "cr_CRE" LOC="P7" | SLEW="fast" | TNM = CR_CTL; +NET "cr_nLB" LOC="K5" | SLEW="fast" | TNM = CR_CTL; +NET "cr_nUB" LOC="K4" | SLEW="fast" | TNM = CR_CTL; +NET "cr_CLK" LOC="H5" | SLEW="fast" | TNM = CR_CTL; + +NET "cr_DQ<0>" LOC="L1" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<1>" LOC="L4" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<2>" LOC="L6" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<3>" LOC="M4" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<4>" LOC="N5" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<5>" LOC="P1" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<6>" LOC="P2" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<7>" LOC="R2" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<8>" LOC="L3" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<9>" LOC="L5" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<10>" LOC="M3" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<11>" LOC="M6" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<12>" LOC="L2" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<13>" LOC="N4" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<14>" LOC="R3" | SLEW="fast" | TNM = CR_DATA; +NET "cr_DQ<15>" LOC="T1" | SLEW="fast" | TNM = CR_DATA; + +NET "cr_A<0>" LOC="J1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<1>" LOC="J2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<2>" LOC="H4" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<3>" LOC="H1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<4>" LOC="H2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<5>" LOC="J5" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<6>" LOC="H3" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<7>" LOC="H6" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<8>" LOC="F1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<9>" LOC="G3" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<10>" LOC="G6" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<11>" LOC="G5" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<12>" LOC="G4" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<13>" LOC="F2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<14>" LOC="E1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<15>" LOC="M5" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<16>" LOC="E2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<17>" LOC="C2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<18>" LOC="C1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<19>" LOC="D2" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<20>" LOC="K3" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<21>" LOC="D1" | SLEW="fast" | TNM = CR_ADDR; +NET "cr_A<22>" LOC="K6" | SLEW="fast" | TNM = CR_ADDR; +NET "st_nCE" LOC="R5" | SLEW="fast" | TNM = CR_CTL; + +NET "vs" LOC = "u3" |SLEW = "fast"; +NET "hs" LOC = "t4" |SLEW = "fast"; +NET "r<2>" LOC = "r8"; +NET "r<1>" LOC = "t8"; +NET "r<0>" LOC = "r9"; +NET "g<2>" LOC = "p6"; +NET "g<1>" LOC = "p8"; +NET "g<0>" LOC = "n8"; +NET "b<1>" LOC = "u4"; +NET "b<0>" LOC = "u5"; + +NET "rst" LOC="H13"; +NET "rstact" LOC="J14"; + +NET "ps2c" LOC="R12" | CLOCK_DEDICATED_ROUTE = FALSE; +NET "ps2d" LOC="P11"; + diff --git a/xst/FireARM.xst b/xst/FireARM.xst index 01b1093..5850e94 100644 --- a/xst/FireARM.xst +++ b/xst/FireARM.xst @@ -5,7 +5,7 @@ run -ifmt mixed -ofn FireARM -ofmt NGC --p xc5vlx110t-1-ff1136 +-p xc3s1200e-5-fg320 -top Console -opt_mode Speed -opt_level 1 diff --git a/xst/Makefile b/xst/Makefile index e4cd3a3..1c86905 100644 --- a/xst/Makefile +++ b/xst/Makefile @@ -1,8 +1,9 @@ TARGET = FireARM -VLOGS = Console.v \ +VLOGS = Console.nexys2.v \ ../ARM_Constants.v \ ../BigBlockRAM.v \ ../BlockRAM.v \ + ../CellularRAM.v \ ../BusArbiter.v \ ../DCache.v \ ../Decode.v \ @@ -41,7 +42,7 @@ BITGEN_OPTS = \ -g Match_cycle:2 \ -g DriveDone:No -fpga_target: $(TARGET).bit +fpga_target: $(TARGET).svf $(TARGET).ngc: $(TARGET).xst $(VLOGS_ALL) @mkdir -p xst/projnav.tmp @@ -71,10 +72,10 @@ sim/%.v: %.ngc netgen -ofmt verilog -w -dir sim $< $(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf - ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc5vlx110t-ff1136-1 "$(TARGET).ngc" $(TARGET).ngd + ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc3s1200e-fg320-5 "$(TARGET).ngc" $(TARGET).ngd $(TARGET)_map.ncd: $(TARGET).ngd - map -w -p xc5vlx110t-ff1136-1 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf + map -w -p xc3s1200e-fg320-5 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf $(TARGET).ncd: $(TARGET)_map.ncd par -w -ol std -t 1 $(TARGET)_map.ncd $(TARGET).ncd $(TARGET).pcf