From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sat, 10 Jan 2009 08:48:06 +0000 (-0500)
Subject: DCache: Fix silly bug involving failing to clear bus_wr.
X-Git-Url: http://git.joshuawise.com/firearm.git/commitdiff_plain/0e3732b3e54e92cd569cd79f41819a7336f1c6ea?ds=inline

DCache: Fix silly bug involving failing to clear bus_wr.
---

diff --git a/DCache.v b/DCache.v
index 4528bd8..e1d5d82 100644
--- a/DCache.v
+++ b/DCache.v
@@ -54,6 +54,11 @@ module DCache(
 	reg [3:0] cache_fill_pos = 0;
 	assign bus_req = (rd_req && !cache_hit) || wr_req;
 	always @(*)
+	begin
+		bus_rd = 0;
+		bus_wr = 0;
+		bus_addr = 0;
+		bus_wdata = 0;
 		if (rd_req && !cache_hit && bus_ack) begin
 			bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
 			bus_rd = 1;
@@ -61,10 +66,8 @@ module DCache(
 			bus_addr = addr;
 			bus_wr = 1;
 			bus_wdata = wr_data;
-		end else begin
-			bus_addr = 0;
-			bus_rd = 0;
 		end
+	end
 	
 	always @(posedge clk)
 		if (rd_req && !cache_hit) begin