Issue, system, RegFile: First pass at adding resets.

diff --git a/Issue.v b/Issue.v
index 153f25f65c85176700001e8f671e8b683bc63dd4..07c709d7ae4aa9335f21122ac12e9dc3f2f47a09 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -279,19 +279,27 @@ module Issue(
        assign outstall = (waiting && !inbubble && !flush) || stall;
 
        reg delayedflush = 0;
-       always @(posedge clk)
-               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+       always @(posedge clk/* or negedge Nrst*/)
+               if (!Nrst)
+                       delayedflush <= 0;
+               else if (flush && outstall /* halp! I can't do it now, maybe later? */)
                        delayedflush <= 1;
                else if (!outstall /* anything has been handled this time around */)
                        delayedflush <= 0;
 
        /* Actually do the issue. */
-       always @(posedge clk)
+       always @(posedge clk or negedge Nrst)
        begin
                if (waiting)
                        $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
 
-               if (!stall)
+               if (!Nrst) begin
+                       cpsr_inflight[0] <= 0;
+                       cpsr_inflight[1] <= 0;
+                       regs_inflight[0] <= 0;
+                       regs_inflight[1] <= 0;
+                       outbubble <= 1;
+               end else if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
                        cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;

diff --git a/RegFile.v b/RegFile.v
index c0e5abdb86954ded9d750a260dcfe6d534ead61b..4ad48dd7f3202548acd56d02aa8c8e525bc544ce 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,5 +1,6 @@
 module RegFile(
        input clk,
+       input Nrst,
        input [3:0] read_0,
        output wire [31:0] rdata_0,
        input [3:0] read_1,
@@ -15,24 +16,11 @@ module RegFile(
        );
        
        reg [31:0] regfile [0:15];
+       integer i;
        
        initial begin
-               regfile[4'h0] = 32'h00000005;
-               regfile[4'h1] = 32'h00000050;
-               regfile[4'h2] = 32'h00000500;
-               regfile[4'h3] = 32'h00005000;
-               regfile[4'h4] = 32'h00050000;
-               regfile[4'h5] = 32'h00500000;
-               regfile[4'h6] = 32'h05000000;
-               regfile[4'h7] = 32'h50000000;
-               regfile[4'h8] = 32'hA0000000;
-               regfile[4'h9] = 32'h0A000000;
-               regfile[4'hA] = 32'h00A00000;
-               regfile[4'hB] = 32'h000A0000;
-               regfile[4'hC] = 32'h0000A000;
-               regfile[4'hD] = 32'h00000A00;
-               regfile[4'hE] = 32'h000000A0;
-               regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
+               for (i = 0; i < 16; i = i + 1)
+                       regfile[i] = 0;
        end
        
        assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0];
@@ -41,7 +29,10 @@ module RegFile(
        assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3];
        assign spsr = regfile[4'hF];
        
-       always @(posedge clk)
-               if (write)
+       always @(posedge clk or negedge Nrst)
+               if (!Nrst) begin
+                       for (i = 0; i < 16; i = i + 1)
+                               regfile[i] <= 0;
+               end else if (write)
                        regfile[write_reg] <= write_data;
 endmodule

diff --git a/ram.hex b/ram.hex
index 6d0fcf570d97a633c5bea08c5f8355ab58d3f505..aa3a6ed2aa1ed74f175e04225010f9aad3b3c869 120000 (symlink)
--- a/ram.hex
+++ b/ram.hex
@@ -1 +1 @@
-tests/testbench.hex
\ No newline at end of file
+tests/testbench.pad.hex
\ No newline at end of file

diff --git a/system.v b/system.v
index f134ffcab95c343545728ea7ede2af0e99103efc..689a0b012826ecc819969658d41e3b9e80c0eb28 100644 (file)
--- a/system.v
+++ b/system.v
@@ -1,7 +1,7 @@
 `define BUS_ICACHE 1
 `define BUS_DCACHE 0
 
-module System(input clk
+module System(input clk, input rst
 `ifdef verilator
 `else
        , output wire [8:0] sys_odata,
@@ -148,7 +148,7 @@ module System(input clk
 
        Fetch fetch(
                .clk(clk),
-               .Nrst(1'b1 /* XXX */),
+               .Nrst(~rst),
                .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
                .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
                .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
@@ -157,7 +157,7 @@ module System(input clk
        
        Issue issue(
                .clk(clk),
-               .Nrst(1'b1 /* XXX */),
+               .Nrst(~rst),
                .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
                .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
                .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
@@ -165,7 +165,7 @@ module System(input clk
                .outpc(pc_out_issue), .outinsn(insn_out_issue));
        
        RegFile regfile(
-               .clk(clk),
+               .clk(clk), .Nrst(~rst),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
                .spsr(regfile_spsr),
@@ -181,7 +181,7 @@ module System(input clk
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        
        Execute execute(
-               .clk(clk), .Nrst(1'b0),
+               .clk(clk), .Nrst(~rst),
                .stall(stall_cause_memory), .flush(writeback_out_backflush),
                .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
                .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
@@ -197,7 +197,7 @@ module System(input clk
        
        assign cp_insn = insn_out_execute;
        Memory memory(
-               .clk(clk), .Nrst(1'b0),
+               .clk(clk), .Nrst(~rst),
                /* stall? */ .flush(writeback_out_backflush),
                .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
                .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),

diff --git a/testbench.cpp b/testbench.cpp
index e89de3851a49f5da9ff6539c19bb6dcf34f2021b..da3d75e9c0ad0c36b0dec6d9d12756ad657c31f7 100644 (file)
--- a/testbench.cpp
+++ b/testbench.cpp
@@ -65,7 +65,7 @@ int main()
        while (!Verilated::gotFinish())
        {
                top->clk = !top->clk;
-               
+               top->rst = 0;
                top->eval();
 //             if (top->clk == 1)
 //                     printf("%d: Bubble: %d. PC: %08x. Ins'n: %08x\n", main_time/2, top->bubbleshield, top->pc, top->insn);