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Execute.v: Add outpc and outinsn. System.v: Add and make wires consistent.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 03:21:53 +0000 (22:21 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 03:21:53 +0000 (22:21 -0500)

No differences found
FireARM pipelined ARM-like CPU implementation in Verilog
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