Makefile: Add 'auto' target to verilog-modeify.

diff --git a/Makefile b/Makefile
index daa9291635be5d55ee231d94b80b3c3bfc82540a..766e6ea09d4008c530fe1bd5ced7f49bcb36ecf4 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -9,4 +9,7 @@ obj_dir/Vsystem.mk: $(VLOGS)
        mkdir -p obj_dir
        verilator --cc system.v testbench.cpp --exe
 
        mkdir -p obj_dir
        verilator --cc system.v testbench.cpp --exe
 

+auto: .DUMMY
+       emacs -l ~/elisp/verilog-mode.el --batch system.v -f verilog-batch-auto
+

 .DUMMY:
\ No newline at end of file
 .DUMMY:
\ No newline at end of file