X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/f83818d545445f70f86a6193ec4f60f9d7e85611..c808669d58509186fededc868210747f78a52933:/icache.v

diff --git a/icache.v b/icache.v
index c09159f..2c29a6c 100644
--- a/icache.v
+++ b/icache.v
@@ -2,10 +2,23 @@
 
 module ICache(
 	input clk,
+	
+	/* ARM core interface */
 	input [31:0] rd_addr,
 	input rd_req,
 	output reg rd_wait,
-	output reg [31:0] rd_data);
+	output reg [31:0] rd_data,
+	
+	/* bus interface */
+	output reg bus_req,
+	input bus_ack,
+	output reg [31:0] bus_addr,
+	input [31:0] bus_data
+	output reg bus_rd,
+	output wire bus_wr,
+	input bus_ready);
+	
+	assign bus_wr = 0;
 	
 	/* [31 tag 10] [9 cache index 6] [5 data index 0]
 	 * so the data index is 6 bits long
@@ -26,8 +39,21 @@ module ICache(
 	wire [3:0] rd_idx = rd_addr[9:6];
 	wire [21:0] rd_tag = rd_addr[31:10];
 	
+	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
+	
 	always @(*) begin	/* XXX does this work nowadays? */
-		rd_wait = !(cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag));
+		rd_wait = !cache_hit;
 		rd_data = cache_data[rd_idx][rd_didx_word];
 	end
+	
+	reg [3:0] cache_fill_pos = 0;
+	reg cache_filling = 0;
+	always @(*) begin
+		if (!cache_hit) begin
+			bus_req = 1;
+			if (bus_ack) begin
+				bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+				bus_rd = 1;
+			end
+		end
 endmodule