X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/ed1fdafee2a20dea5a6e7f25f1395443313d0986..1e7ff543e49341fedea742d7b8b674111d852748:/system.v

diff --git a/system.v b/system.v
index 99680aa..97880c9 100644
--- a/system.v
+++ b/system.v
@@ -6,7 +6,12 @@ module System(input clk, input rst
 `else
 	, output wire [8:0] sys_odata,
 	input [8:0] sys_idata,
-	output wire sys_tookdata
+	output wire sys_tookdata,
+
+	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+	inout wire [15:0] cr_DQ,
+	output wire [22:0] cr_A,
+	output wire st_nCE
 `endif
 	);
 	
@@ -34,15 +39,15 @@ module System(input clk, input rst
 	wire bus_rd_dcache;
 	wire bus_wr_dcache;
 	
-	wire [31:0] bus_rdata_blockram;
-	wire bus_ready_blockram;
+	wire [31:0] bus_rdata_blockram, bus_rdata_cellularram;
+	wire bus_ready_blockram, bus_ready_cellularram;
 	
 	assign bus_addr = bus_addr_icache | bus_addr_dcache;
-	assign bus_rdata = bus_rdata_blockram;
+	assign bus_rdata = bus_rdata_blockram | bus_rdata_cellularram;
 	assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
 	assign bus_rd = bus_rd_icache | bus_rd_dcache;
 	assign bus_wr = bus_wr_icache | bus_wr_dcache;
-	assign bus_ready = bus_ready_blockram;
+	assign bus_ready = bus_ready_blockram | bus_ready_cellularram;
 
 	wire [31:0] icache_rd_addr;
 	wire icache_rd_req;
@@ -239,6 +244,40 @@ module System(input clk, input rst
 		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
 		.bus_ready(bus_ready_blockram));
 
+`ifdef verilator
+	assign bus_rdata_cellularram = 32'h00000000;
+	assign bus_ready_cellularram = 0;
+`else
+	/* CellularRAM AUTO_TEMPLATE (
+		.bus_rdata(bus_rdata_cellularram),
+		.bus_ready(bus_ready_cellularram),
+		);
+	*/
+	CellularRAM cellularram(
+		/*AUTOINST*/
+				// Outputs
+				.bus_rdata	(bus_rdata_cellularram), // Templated
+				.bus_ready	(bus_ready_cellularram), // Templated
+				.cr_nADV	(cr_nADV),
+				.cr_nCE		(cr_nCE),
+				.cr_nOE		(cr_nOE),
+				.cr_nWE		(cr_nWE),
+				.cr_CRE		(cr_CRE),
+				.cr_nLB		(cr_nLB),
+				.cr_nUB		(cr_nUB),
+				.cr_CLK		(cr_CLK),
+				.cr_A		(cr_A[22:0]),
+				.st_nCE		(st_nCE),
+				// Inouts
+				.cr_DQ		(cr_DQ[15:0]),
+				// Inputs
+				.clk		(clk),
+				.bus_addr	(bus_addr[31:0]),
+				.bus_wdata	(bus_wdata[31:0]),
+				.bus_rd		(bus_rd),
+				.bus_wr		(bus_wr));
+`endif
+
 	/* Fetch AUTO_TEMPLATE (
 		.jmp_0a(jmp),
 		.jmppc_0a(jmppc),
@@ -382,7 +421,7 @@ module System(input clk, input rst
 			.carry_2a	(carry_2a));
 	assign execute_out_backflush = jmp;
 	
-	assign cp_insn = insn_out_execute;
+	assign cp_insn = insn_3a;
 	/* stall? */
 	/* Memory AUTO_TEMPLATE (
 		.flush(writeback_out_backflush),
@@ -477,7 +516,7 @@ module System(input clk, input rst
 		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
 		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
 		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
-		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
+		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_3a, insn_3a, pc_3a, write_reg_3a, write_data_3a, write_num_3a, jmp_out_execute, jmppc_out_execute);
 		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
 		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
 	end