X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/dfe0713aebc58dd093c309011ac0596597ab2cb5..b0e4ff00b849c456433c85da7c6049c075c8f0f6:/RegFile.v?ds=inline

diff --git a/RegFile.v b/RegFile.v
index 730a620..836eae4 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,66 +1,38 @@
 module RegFile(
-	input clk,
-	input [3:0] read_0,
-	output reg [31:0] rdata_0,
-	input [3:0] read_1,
-	output reg [31:0] rdata_1,
-	input [3:0] read_2,
-	output reg [31:0] rdata_2,
-	input [3:0] read_3,
-	output reg [31:0] rdata_3,
-	output reg [31:0] spsr,
-	input write,
-	input [3:0] write_reg,
-	input [31:0] write_data
+	input              clk,
+	input              Nrst,
+	input        [3:0] rf__read_0_1a,
+	output wire [31:0] rf__rdata_0_1a,
+	input        [3:0] rf__read_1_1a,
+	output wire [31:0] rf__rdata_1_1a,
+	input        [3:0] rf__read_2_1a,
+	output wire [31:0] rf__rdata_2_1a,
+	input        [3:0] rf__read_3_4a,
+	output wire [31:0] rf__rdata_3_4a,
+	output wire [31:0] spsr,
+	input              write,
+	input        [3:0] write_reg,
+	input       [31:0] write_data
 	);
 	
 	reg [31:0] regfile [0:15];
+	integer i;
 	
 	initial begin
-		regfile[4'h0] = 32'h00000005;
-		regfile[4'h1] = 32'h00000050;
-		regfile[4'h2] = 32'h00000500;
-		regfile[4'h3] = 32'h00005000;
-		regfile[4'h4] = 32'h00050000;
-		regfile[4'h5] = 32'h00500000;
-		regfile[4'h6] = 32'h05000000;
-		regfile[4'h7] = 32'h50000000;
-		regfile[4'h8] = 32'hA0000000;
-		regfile[4'h9] = 32'h0A000000;
-		regfile[4'hA] = 32'h00A00000;
-		regfile[4'hB] = 32'h000A0000;
-		regfile[4'hC] = 32'h0000A000;
-		regfile[4'hD] = 32'h00000A00;
-		regfile[4'hE] = 32'h000000A0;
-		regfile[4'hF] = 32'h00000000;	/* Start off claiming we are in user mode. */
+		for (i = 0; i < 16; i = i + 1)
+			regfile[i] = 0;
 	end
 	
-	always @(*)
-	begin
-		if ((read_0 == write_reg) && write)
-			rdata_0 = write_data;
-		else
-			rdata_0 = regfile[read_0];
-		
-		if ((read_1 == write_reg) && write)
-			rdata_1 = write_data;
-		else
-			rdata_1 = regfile[read_1];
-		
-		if ((read_2 == write_reg) && write)
-			rdata_2 = write_data;
-		else
-			rdata_2 = regfile[read_2];
-
-		if ((read_3 == write_reg) && write)
-			rdata_3 = write_data;
-		else
-			rdata_3 = regfile[read_3];
-		
-		spsr = regfile[4'hF];
-	end
+	assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a];
+	assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a];
+	assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a];
+	assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a];
+	assign spsr = regfile[4'hF];
 	
-	always @(posedge clk)
-		if (write)
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst) begin
+			for (i = 0; i < 16; i = i + 1)
+				regfile[i] <= 0;
+		end else if (write)
 			regfile[write_reg] <= write_data;
 endmodule