X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/dfe0713aebc58dd093c309011ac0596597ab2cb5..95704fd3cfedb792839f6168c777d77ca1da3ceb:/Memory.v

diff --git a/Memory.v b/Memory.v
index eb4006f..2e6ed0f 100644
--- a/Memory.v
+++ b/Memory.v
@@ -23,7 +23,7 @@ module Memory(
 	output reg cp_req,
 	input cp_ack,
 	input cp_busy,
-	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
+	output reg cp_rnw,	/* 1 = read from CP, 0 = write to CP */
 	input [31:0] cp_read,
 	output reg [31:0] cp_write,
 	
@@ -57,10 +57,10 @@ module Memory(
 	reg [3:0] next_regsel, cur_reg, prev_reg;
 	reg next_writeback;
 
-	wire next_outbubble;	
-	wire next_write_reg;
-	wire [3:0] next_write_num;
-	wire [31:0] next_write_data;
+	reg next_outbubble;	
+	reg next_write_reg;
+	reg [3:0] next_write_num;
+	reg [31:0] next_write_data;
 
 	reg [1:0] lsr_state = 2'b01, next_lsr_state;
 	reg [31:0] align_s1, align_s2, align_rddata;
@@ -87,7 +87,8 @@ module Memory(
 		out_write_data <= next_write_data;
 		regs <= next_regs;
 		prev_reg <= cur_reg;
-		prev_offset <= offset;
+		if (!rw_wait)
+			prev_offset <= offset;
 		prev_raddr <= raddr;
 		outcpsr <= next_outcpsr;
 		outspsr <= spsr;
@@ -97,6 +98,13 @@ module Memory(
 		lsrh_state <= next_lsrh_state;
 		prevaddr <= addr;
 	end
+	
+	reg delayedflush = 0;
+	always @(posedge clk)
+		if (flush && outstall /* halp! I can't do it now, maybe later? */)
+			delayedflush <= 1;
+		else if (!outstall /* anything has been handled this time around */)
+			delayedflush <= 0;
 
 	always @(*)
 	begin
@@ -129,9 +137,7 @@ module Memory(
 		cur_reg = prev_reg;
 
 		/* XXX shit not given about endianness */
-		if (flush)
-			next_outbubble = 1'b1;
-		else casez(insn)
+		casez(insn)
 		`DECODE_ALU_SWP: if(!inbubble) begin
 			outstall = rw_wait;
 			next_outbubble = rw_wait;
@@ -216,7 +222,7 @@ module Memory(
 			next_outbubble = rw_wait;
 			outstall = rw_wait;
 			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
-			raddr = insn[24] ? op0 : addr; /* pre/post increment */
+			raddr = insn[24] ? addr : op0; /* pre/post increment */
 			busaddr = raddr;
 			/* rotate to correct position */
 			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
@@ -239,12 +245,13 @@ module Memory(
 					if(!rw_wait)
 						next_lsr_state = 2'b10;
 				end
+				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
 			end
 			2'b10: begin
 				next_write_reg = 1'b1;
 				next_write_num = insn[19:16];
 				next_write_data = addr;
-				next_lsr_state = 2'b10;
+				next_lsr_state = 2'b01;
 			end
 			default: begin end
 			endcase
@@ -258,8 +265,9 @@ module Memory(
 			3'b001: begin
 //				next_regs = insn[23] ? op1[15:0] : op1[0:15];
 				/** verilator can suck my dick */
-				next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
-				                                    op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+				$display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
+				next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+				                                            op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
 				offset = 6'b0;
 				outstall = 1'b1;
 				next_lsm_state = 3'b010;
@@ -337,30 +345,29 @@ module Memory(
 					next_regs = 16'b0;
 				end
 				endcase
-				cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
+				cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
 				if(cur_reg == 4'hF && insn[22]) begin
 					next_outcpsr = spsr;
 				end
 
-				if(rw_wait) begin
-					next_regs = regs;
-					cur_reg = prev_reg;
-					raddr = prev_raddr;
+				offset = prev_offset + 6'h4;
+				offset_sel = insn[24] ? offset : prev_offset;
+				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+				if(insn[20]) begin
+					next_write_reg = !rw_wait;
+					next_write_num = cur_reg;
+					next_write_data = rd_data;
 				end
-				else begin
-					offset = prev_offset + 6'h4;
-					offset_sel = insn[24] ? offset : prev_offset;
-					raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
-					if(insn[20]) begin
-						next_write_reg = 1'b1;
-						next_write_num = cur_reg;
-						next_write_data = rd_data;
-					end
+				if (rw_wait) begin
+					next_regs = regs;
+					cur_reg = prev_reg;	/* whoops, do this one again */
 				end
 
 				st_read = cur_reg;
-				wr_data = st_data;
+				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
 				busaddr = raddr;
+				
+				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
 
 				outstall = 1'b1;
 
@@ -369,13 +376,15 @@ module Memory(
 				end
 			end
 			3'b100: begin
-				next_write_reg = 1'b1;
+				next_write_reg = insn[21] /* writeback */;
 				next_write_num = insn[19:16];
 				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
 				next_lsm_state = 3'b001;
+				$display("LDMSTM: Stage 3: Writing back");
 			end
-			default: begin end
+			default: $stop;
 			endcase
+			$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
 		end
 		`DECODE_LDCSTC: if(!inbubble) begin
 			$display("WARNING: Unimplemented LDCSTC");
@@ -415,5 +424,8 @@ module Memory(
 		end
 		default: begin end
 		endcase
+		
+		if ((flush || delayedflush) && !outstall)
+			next_outbubble = 1'b1;
 	end
 endmodule