X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/d43b0ab9a916f24601dd987fa84eb6e629b1679d..ed1fdafee2a20dea5a6e7f25f1395443313d0986:/Fetch.v

diff --git a/Fetch.v b/Fetch.v
index aa9bd7c..bc2175c 100644
--- a/Fetch.v
+++ b/Fetch.v
@@ -1,54 +1,70 @@
 module Fetch(
-	input clk,
-	input Nrst,
+	input              clk,
+	input              Nrst,
 	
-	output wire [31:0] rd_addr,
-	output wire rd_req,
-	input rd_wait,
-	input [31:0] rd_data,
+	output wire [31:0] ic__rd_addr_0a,
+	output wire        ic__rd_req_0a,
+	input              ic__rd_wait_0a,
+	input       [31:0] ic__rd_data_1a,
 	
-	input stall,
-	input jmp,
-	input [31:0] jmppc,
-	output reg bubble = 1,
-	output reg [31:0] insn = 0,
-	output reg [31:0] pc = 32'hFFFFFFFC);
+	input              stall_0a,
+	input              jmp_0a,
+	input       [31:0] jmppc_0a,
+	output reg         bubble_1a = 1,
+	output reg  [31:0] insn_1a = 0,
+	output reg  [31:0] pc_1a = 32'hFFFFFFFC);
 	
 	reg qjmp = 0;	/* A jump has been queued up while we were waiting. */
 	reg [31:0] qjmppc;
 	always @(posedge clk or negedge Nrst)
 		if (!Nrst)
 			qjmp <= 0;
-		else if ((rd_wait || stall) && jmp)
-			{qjmp,qjmppc} <= {jmp, jmppc};
-		else if (!rd_wait && !stall && qjmp)	/* It has already been intoed. */
+		else if ((ic__rd_wait_0a || stall_0a) && jmp_0a)
+			{qjmp,qjmppc} <= {jmp_0a, jmppc_0a};
+		else if (!ic__rd_wait_0a && !stall_0a && qjmp)	/* It has already been intoed. */
 			{qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
 	
-	reg [31:0] reqpc;
+	reg [31:0] reqpc_0a;
+	
+	/* Output latch logic */
+	reg [31:0] insn_2a;
+	reg stall_1a;
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst) begin
+			insn_2a <= 32'h00000000;
+			stall_1a <= 0;
+		end else begin
+			insn_2a <= insn_1a;
+			stall_1a <= stall_0a;
+		end
+	
 	always @(*)
-		if (stall)
-			reqpc = pc;
-		else if (qjmp)
-			reqpc = qjmppc;
-		else if (jmp)
-			reqpc = jmppc;
+		if (stall_1a)
+			insn_1a = insn_2a;
 		else
-			reqpc = pc + 4;
+			insn_1a = ic__rd_data_1a;
 	
-	assign rd_addr = reqpc;
-	assign rd_req = 1;
+	assign ic__rd_addr_0a = reqpc_0a;
+	assign ic__rd_req_0a = 1;
 	
 	always @(posedge clk or negedge Nrst)
-	begin
 		if (!Nrst) begin
-			pc <= 32'hFFFFFFFC;
-			bubble <= 1;
-		end else if (!stall)
-		begin
-			bubble <= rd_wait;
-			insn <= rd_data;
-			if (!rd_wait)
-				pc <= reqpc;
+			bubble_1a <= 1;
+			pc_1a <= 32'h00000000;
+		end else if (!stall_0a) begin
+			bubble_1a <= (jmp_0a || qjmp || ic__rd_wait_0a);
+			pc_1a <= reqpc_0a;
+		end
+	
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst)
+			reqpc_0a <= 0;
+		else if (!stall_0a && !ic__rd_wait_0a) begin
+			if (qjmp)
+				reqpc_0a <= qjmppc;
+			else if (jmp_0a)
+				reqpc_0a <= jmppc_0a;
+			else
+				reqpc_0a <= reqpc_0a + 4;
 		end
-	end
 endmodule