X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/cb0428b6a01af21f4c98bb827405d18239a1f97f..b45b7b7cecfef2b61eb74a6047c6994a100299be:/RegFile.v

diff --git a/RegFile.v b/RegFile.v
index 95e5c71..730a620 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,9 +6,11 @@ module RegFile(
 	output reg [31:0] rdata_1,
 	input [3:0] read_2,
 	output reg [31:0] rdata_2,
+	input [3:0] read_3,
+	output reg [31:0] rdata_3,
 	output reg [31:0] spsr,
-	input [3:0] write,
-	input write_req,
+	input write,
+	input [3:0] write_reg,
 	input [31:0] write_data
 	);
 	
@@ -35,25 +37,30 @@ module RegFile(
 	
 	always @(*)
 	begin
-		if ((read_0 == write) && write_req)
+		if ((read_0 == write_reg) && write)
 			rdata_0 = write_data;
 		else
 			rdata_0 = regfile[read_0];
 		
-		if ((read_1 == write) && write_req)
+		if ((read_1 == write_reg) && write)
 			rdata_1 = write_data;
 		else
 			rdata_1 = regfile[read_1];
 		
-		if ((read_2 == write) && write_req)
+		if ((read_2 == write_reg) && write)
 			rdata_2 = write_data;
 		else
 			rdata_2 = regfile[read_2];
+
+		if ((read_3 == write_reg) && write)
+			rdata_3 = write_data;
+		else
+			rdata_3 = regfile[read_3];
 		
 		spsr = regfile[4'hF];
 	end
 	
 	always @(posedge clk)
-		if (write_req)
-			regfile[write] <= write_data;
+		if (write)
+			regfile[write_reg] <= write_data;
 endmodule