X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/c65110a8c83463c0f95391c2ec7e0277de333c62..HEAD:/Execute.v diff --git a/Execute.v b/Execute.v index 7f4cf6c..4420a75 100644 --- a/Execute.v +++ b/Execute.v @@ -2,31 +2,32 @@ module Execute( input clk, input Nrst, /* XXX not used yet */ - input stall, - input flush, + input stall_2a, + input flush_2a, - input inbubble, - input [31:0] pc, - input [31:0] insn, - input [31:0] cpsr, - input [31:0] spsr, - input [31:0] op0, - input [31:0] op1, - input [31:0] op2, - input carry, + input bubble_2a, + input [31:0] pc_2a, + input [31:0] insn_2a, + input [31:0] cpsr_2a, + input [31:0] spsr_2a, + input [31:0] op0_2a, + input [31:0] op1_2a, + input [31:0] op2_2a, + input carry_2a, - output reg outstall = 0, - output reg outbubble = 1, - output reg [31:0] outcpsr = 0, - output reg [31:0] outspsr = 0, - output reg write_reg = 1'bx, - output reg [3:0] write_num = 4'bxxxx, - output reg [31:0] write_data = 32'hxxxxxxxx, - output reg [31:0] jmppc, - output reg jmp, - output reg [31:0] outpc, - output reg [31:0] outinsn, - output reg [31:0] outop0, outop1, outop2 + output reg outstall_2a = 0, + output reg bubble_3a = 1, + output reg [31:0] cpsr_3a = 0, + output reg [31:0] spsr_3a = 0, + output reg cpsrup_3a = 0, + output reg write_reg_3a = 1'bx, + output reg [3:0] write_num_3a = 4'bxxxx, + output reg [31:0] write_data_3a = 32'hxxxxxxxx, + output reg [31:0] jmppc_2a, + output reg jmp_2a, + output reg [31:0] pc_3a, + output reg [31:0] insn_3a, + output reg [31:0] op0_3a, op1_3a, op2_3a ); reg mult_start; @@ -34,18 +35,19 @@ module Execute( wire mult_done; wire [31:0] mult_result; - reg [31:0] alu_in0, alu_in1; - reg [3:0] alu_op; - reg alu_setflags; - wire [31:0] alu_result, alu_outcpsr; - wire alu_setres; + reg [31:0] alu_in0_2a, alu_in1_2a; + reg [3:0] alu_op_2a; + reg alu_setflags_2a; + wire [31:0] alu_result_2a, alu_outcpsr_2a; + wire alu_setres_2a; - reg next_outbubble; - reg [31:0] next_outcpsr, next_outspsr; - reg next_write_reg; - reg [3:0] next_write_num; - - reg [31:0] next_write_data; + reg next_bubble_3a; + reg [31:0] next_cpsr_3a, next_spsr_3a; + reg next_cpsrup_3a; + + reg next_write_reg_3a; + reg [3:0] next_write_num_3a; + reg [31:0] next_write_data_3a; Multiplier multiplier( .clk(clk), .Nrst(Nrst), @@ -54,97 +56,104 @@ module Execute( ALU alu( .clk(clk), .Nrst(Nrst), - .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op), - .setflags(alu_setflags), .shifter_carry(carry), - .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres)); - + .in0(alu_in0_2a), .in1(alu_in1_2a), .cpsr(cpsr_2a), .op(alu_op_2a), + .setflags(alu_setflags_2a), .shifter_carry(carry_2a), + .result(alu_result_2a), .cpsr_out(alu_outcpsr_2a), .setres(alu_setres_2a)); + always @(posedge clk) begin - if (!stall) + if (!stall_2a) begin - outbubble <= next_outbubble; - outcpsr <= next_outcpsr; - outspsr <= next_outspsr; - write_reg <= next_write_reg; - write_num <= next_write_num; - write_data <= next_write_data; - outpc <= pc; - outinsn <= insn; - outop0 <= op0; - outop1 <= op1; - outop2 <= op2; + bubble_3a <= next_bubble_3a; + cpsr_3a <= next_cpsr_3a; + spsr_3a <= next_spsr_3a; + cpsrup_3a <= next_cpsrup_3a; + write_reg_3a <= next_write_reg_3a; + write_num_3a <= next_write_num_3a; + write_data_3a <= next_write_data_3a; + pc_3a <= pc_2a; + insn_3a <= insn_2a; + op0_3a <= op0_2a; + op1_3a <= op1_2a; + op2_3a <= op2_2a; end end - - reg prevstall = 0; + + reg delayedflush_2a = 0; always @(posedge clk) - prevstall <= outstall; + if (flush_2a && outstall_2a /* halp! I can't do it now, maybe later? */) + delayedflush_2a <= 1; + else if (!outstall_2a /* anything has been handled this time around */) + delayedflush_2a <= 0; + reg outstall_3a = 0; + always @(posedge clk) + outstall_3a <= outstall_2a; + always @(*) begin - outstall = stall; - next_outbubble = inbubble | flush; - next_outcpsr = cpsr; - next_outspsr = spsr; - next_write_reg = 0; - next_write_num = 4'hx; - next_write_data = 32'hxxxxxxxx; - - mult_start = 0; - mult_acc0 = 32'hxxxxxxxx; - mult_in0 = 32'hxxxxxxxx; - mult_in1 = 32'hxxxxxxxx; - - alu_in0 = 32'hxxxxxxxx; - alu_in1 = 32'hxxxxxxxx; - alu_op = 4'hx; /* hax! */ - alu_setflags = 1'bx; - - jmp = 1'b0; - jmppc = 32'hxxxxxxxx; - - casez (insn) + outstall_2a = stall_2a; + + casez (insn_2a) + `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ + outstall_2a = outstall_2a | ((!outstall_3a | !mult_done) && !bubble_2a); + endcase + end + + /* ALU inputs */ + always @(*) + begin + alu_in0_2a = op0_2a; + alu_in1_2a = op1_2a; + alu_op_2a = insn_2a[24:21]; + alu_setflags_2a = insn_2a[20] /* S */; + end + + /* Register outputs */ + always @(*) + begin + next_cpsr_3a = cpsr_2a; + next_spsr_3a = spsr_2a; + next_cpsrup_3a = 0; + next_write_reg_3a = 0; + next_write_num_3a = 4'hx; + next_write_data_3a = 32'hxxxxxxxx; + + casez(insn_2a) `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ begin - if (!prevstall && !inbubble) - begin - mult_start = 1; - mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0; - mult_in0 = op1 /* Rm */; - mult_in1 = op2 /* Rs */; - $display("New MUL instruction"); - end - outstall = stall | ((!prevstall | !mult_done) && !inbubble); - next_outbubble = inbubble | !mult_done | !prevstall; - next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr; - next_write_reg = 1; - next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */; - next_write_data = mult_result; + next_cpsr_3a = insn_2a[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr_2a[28] /* V */, cpsr_2a[27:0]} : cpsr_2a; + next_cpsrup_3a = insn_2a[20] /* S */; + next_write_reg_3a = 1; + next_write_num_3a = insn_2a[19:16] /* Rd -- why the fuck isn't this the same place as ALU */; + next_write_data_3a = mult_result; end -// `DECODE_ALU_MUL_LONG, /* Multiply long */ `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */ begin - next_write_reg = 1; - next_write_num = insn[15:12]; - if (insn[22] /* Ps */) - next_write_data = spsr; + next_write_reg_3a = 1; + next_write_num_3a = insn_2a[15:12]; + if (insn_2a[22] /* Ps */) + next_write_data_3a = spsr_2a; else - next_write_data = cpsr; + next_write_data_3a = cpsr_2a; end `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */ `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */ - if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0)) /* flags only */ + begin + if ((cpsr_2a[4:0] == `MODE_USR) || (insn_2a[16] /* that random bit */ == 1'b0)) /* flags only */ begin - if (insn[22] /* Ps */) - next_outspsr = {op0[31:29], spsr[28:0]}; + if (insn_2a[22] /* Ps */) + next_spsr_3a = {op0_2a[31:29], spsr_2a[28:0]}; else - next_outcpsr = {op0[31:29], cpsr[28:0]}; + next_cpsr_3a = {op0_2a[31:29], cpsr_2a[28:0]}; end else begin - if (insn[22] /* Ps */) - next_outspsr = op0; + if (insn_2a[22] /* Ps */) + next_spsr_3a = op0_2a; else - next_outcpsr = op0; + next_cpsr_3a = op0_2a; end + next_cpsrup_3a = 1; + end `DECODE_ALU_SWP, /* Atomic swap */ `DECODE_ALU_BX, /* Branch */ `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */ @@ -152,33 +161,83 @@ module Execute( begin end `DECODE_ALU: /* ALU */ begin - alu_in0 = op0; - alu_in1 = op1; - alu_op = insn[24:21]; - alu_setflags = insn[20] /* S */; - - if (alu_setres) begin - next_write_reg = 1; - next_write_num = insn[15:12] /* Rd */; - next_write_data = alu_result; + if (alu_setres_2a) begin + next_write_reg_3a = 1; + next_write_num_3a = insn_2a[15:12] /* Rd */; + next_write_data_3a = alu_result_2a; end - next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr; + if (insn_2a[20] /* S */) begin + next_cpsrup_3a = 1; + next_cpsr_3a = ((insn_2a[15:12] == 4'b1111) && insn_2a[20]) ? spsr_2a : alu_outcpsr_2a; + end + end + `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */ + `DECODE_LDRSTR, /* Single data transfer */ + `DECODE_LDMSTM: /* Block data transfer */ + begin end + `DECODE_BRANCH: /* Branch */ + begin + if(insn_2a[24] /* L */) begin + next_write_reg_3a = 1; + next_write_num_3a = 4'hE; /* link register */ + next_write_data_3a = pc_2a + 32'h4; + end + end + endcase + end + + /* Multiplier inputs */ + always @(*) + begin + mult_start = 0; + mult_acc0 = 32'hxxxxxxxx; + mult_in0 = 32'hxxxxxxxx; + mult_in1 = 32'hxxxxxxxx; + + casez(insn_2a) + `DECODE_ALU_MULT: + begin + if (!outstall_3a /* i.e., this is a new one */ && !bubble_2a /* i.e., this is a real one */) + begin + mult_start = 1; + mult_acc0 = insn_2a[21] /* A */ ? op0_2a /* Rn */ : 32'h0; + mult_in0 = op1_2a /* Rm */; + mult_in1 = op2_2a /* Rs */; + $display("New MUL instruction"); + end end + endcase + end + + /* Miscellaneous cleanup. */ + always @(*) + begin + next_bubble_3a = bubble_2a | flush_2a | delayedflush_2a; + + jmp_2a = 1'b0; + jmppc_2a = 32'h00000000; + + casez (insn_2a) + `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ + next_bubble_3a = next_bubble_3a | !mult_done | !outstall_3a; + `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */ + `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */ + `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */ + `DECODE_ALU_SWP, /* Atomic swap */ + `DECODE_ALU_BX, /* Branch */ + `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */ + `DECODE_ALU_HDATA_IMM, /* Halfword transfer - immediate offset */ + `DECODE_ALU, /* ALU */ `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */ `DECODE_LDRSTR, /* Single data transfer */ `DECODE_LDMSTM: /* Block data transfer */ begin end `DECODE_BRANCH: begin - if(!inbubble) begin - jmppc = pc + op0 + 32'h8; - if(insn[24]) begin - next_write_reg = 1; - next_write_num = 4'hE; /* link register */ - next_write_data = pc - 32'h4; - end - jmp = 1'b1; + if(!bubble_2a && !flush_2a && !delayedflush_2a && !outstall_2a /* Let someone else take precedence. */) begin + jmppc_2a = pc_2a + op0_2a + 32'h8; + jmp_2a = 1'b1; end end /* Branch */ `DECODE_LDCSTC, /* Coprocessor data transfer */ @@ -251,7 +310,7 @@ module ALU( assign sum = {1'b0, in0} + {1'b0, in1}; assign diff = {1'b0, in0} - {1'b0, in1}; - assign rdiff = {1'b0, in1} + {1'b0, in0}; + assign rdiff = {1'b0, in1} - {1'b0, in0}; assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]); assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]); assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]); @@ -274,11 +333,13 @@ module ALU( end `ALU_SUB: begin {flag_c, result} = diff; + flag_c = !flag_c; flag_v = diff_v; setres = 1'b1; end `ALU_RSB: begin {flag_c, result} = rdiff; + flag_c = !flag_c; flag_v = rdiff_v; setres = 1'b1; end @@ -294,11 +355,13 @@ module ALU( end `ALU_SBC: begin {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])}; + flag_c = !flag_c; flag_v = diff_v | (diff[31] & ~result[31]); setres = 1'b1; end `ALU_RSC: begin {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])}; + flag_c = !flag_c; flag_v = rdiff_v | (rdiff[31] & ~result[31]); setres = 1'b1; end @@ -314,6 +377,7 @@ module ALU( end `ALU_CMP: begin {flag_c, result} = diff; + flag_c = !flag_c; flag_v = diff_v; setres = 1'b0; end