X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/c4e2ac3b3f80b9d92660c87009714362cdb7f875..ab12fa63de15b711788d5f09927ba5955a3f0bee:/Issue.v?ds=inline diff --git a/Issue.v b/Issue.v index 7815a08..07c709d 100644 --- a/Issue.v +++ b/Issue.v @@ -12,7 +12,7 @@ module Issue( input [31:0] inpc, input [31:0] cpsr, - output reg outstall = 0, /* stage outputs */ + output wire outstall, /* stage outputs */ output reg outbubble = 1, output reg [31:0] outpc = 0, output reg [31:0] outinsn = 0 @@ -180,7 +180,7 @@ module Issue( `DECODE_LDRSTR: begin use_cpsr = `COND_MATTERS(cond); - use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd)); + use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd)); def_cpsr = 0; def_regs = insn[20] /* L */ ? idxbit(rd) : 0; end @@ -196,7 +196,7 @@ module Issue( use_cpsr = `COND_MATTERS(cond); use_regs = 0; def_cpsr = 0; - def_regs = 0; + def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0; end `DECODE_LDCSTC: /* Coprocessor data transfer */ begin @@ -265,10 +265,6 @@ module Issue( reg cpsr_inflight [1:0]; reg [15:0] regs_inflight [1:0]; - reg waiting_cpsr; - reg waiting_regs; - wire waiting = waiting_cpsr | waiting_regs; - initial begin cpsr_inflight[0] = 0; @@ -276,44 +272,41 @@ module Issue( regs_inflight[0] = 0; regs_inflight[1] = 0; end - - always @(*) - begin - waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); - waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); - - outstall = (waiting && !inbubble && !flush) || stall; /* Happens in an always @*, because it is an exception. */ - end + + wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); + wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); + wire waiting = waiting_cpsr | waiting_regs; + assign outstall = (waiting && !inbubble && !flush) || stall; reg delayedflush = 0; - always @(posedge clk) - if (flush && outstall /* halp! I can't do it now, maybe later? */) + always @(posedge clk/* or negedge Nrst*/) + if (!Nrst) + delayedflush <= 0; + else if (flush && outstall /* halp! I can't do it now, maybe later? */) delayedflush <= 1; else if (!outstall /* anything has been handled this time around */) delayedflush <= 0; - + /* Actually do the issue. */ - always @(posedge clk) + always @(posedge clk or negedge Nrst) begin if (waiting) $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs); - if((flush || delayedflush) && !outstall) - begin - cpsr_inflight[0] = 1'b0; - cpsr_inflight[1] = 1'b0; - regs_inflight[0] = 16'b0; - regs_inflight[1] = 16'b0; - outbubble <= 1'b1; - end - else if (!stall) + if (!Nrst) begin + cpsr_inflight[0] <= 0; + cpsr_inflight[1] <= 0; + regs_inflight[0] <= 0; + regs_inflight[1] <= 0; + outbubble <= 1; + end else if (!stall) begin cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */ cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr; regs_inflight[0] <= regs_inflight[1]; regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs; - outbubble <= inbubble | waiting | !condition_met; + outbubble <= inbubble | waiting | !condition_met | flush | delayedflush; outpc <= inpc; outinsn <= insn; end