X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/b957d34df393c6b39548629c0f1272175173d6b9..fb529aac5eac18b5f4b10cb8c7265997ac253a65:/Memory.v

diff --git a/Memory.v b/Memory.v
index 5403275..c709e83 100644
--- a/Memory.v
+++ b/Memory.v
@@ -87,7 +87,8 @@ module Memory(
 		out_write_data <= next_write_data;
 		regs <= next_regs;
 		prev_reg <= cur_reg;
-		prev_offset <= offset;
+		if (!rw_wait)
+			prev_offset <= offset;
 		prev_raddr <= raddr;
 		outcpsr <= next_outcpsr;
 		outspsr <= spsr;
@@ -97,6 +98,13 @@ module Memory(
 		lsrh_state <= next_lsrh_state;
 		prevaddr <= addr;
 	end
+	
+	reg delayedflush = 0;
+	always @(posedge clk)
+		if (flush && outstall /* halp! I can't do it now, maybe later? */)
+			delayedflush <= 1;
+		else if (!outstall /* anything has been handled this time around */)
+			delayedflush <= 0;
 
 	always @(*)
 	begin
@@ -129,9 +137,7 @@ module Memory(
 		cur_reg = prev_reg;
 
 		/* XXX shit not given about endianness */
-		if (flush)
-			next_outbubble = 1'b1;
-		else casez(insn)
+		casez(insn)
 		`DECODE_ALU_SWP: if(!inbubble) begin
 			outstall = rw_wait;
 			next_outbubble = rw_wait;
@@ -145,6 +151,7 @@ module Memory(
 					next_swp_state = 2'b10;
 					next_swp_oldval = rd_data;
 				end
+				$display("SWP: read stage");
 			end
 			2'b10: begin
 				wr_req = 1'b1;
@@ -154,10 +161,12 @@ module Memory(
 				next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
 				if(!rw_wait)
 					next_swp_state = 2'b01;
+				$display("SWP: write stage");
 			end
 			default: begin end
 			endcase
 		end
+		`DECODE_ALU_MULT: begin end
 		`DECODE_ALU_HDATA_REG,
 		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
 			next_outbubble = rw_wait;
@@ -201,6 +210,7 @@ module Memory(
 					if(!rw_wait)
 						next_lsrh_state = 2'b10;
 				end
+				$display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
 			end
 			2'b10: begin
 				next_write_reg = 1'b1;
@@ -227,18 +237,19 @@ module Memory(
 			data_size = insn[22] ? 3'b001 : 3'b100;
 			case(lsr_state)
 			2'b01: begin
-				rd_req = insn[20];
-				wr_req = ~insn[20];
-				next_write_reg = 1'b1;
+				rd_req = insn[20] /* L */;
+				wr_req = ~insn[20] /* L */;
+				next_write_reg = insn[20] /* L */;
 				next_write_num = insn[15:12];
-				if(insn[20]) begin
+				if(insn[20] /* L */) begin
 					next_write_data = align_rddata;
 				end
-				if(insn[21] | !insn[24]) begin
+				if(insn[21] /* W */ | !insn[24] /* P */) begin
 					outstall = 1'b1;
 					if(!rw_wait)
 						next_lsr_state = 2'b10;
 				end
+				$display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
 			end
 			2'b10: begin
 				next_write_reg = 1'b1;
@@ -343,27 +354,24 @@ module Memory(
 					next_outcpsr = spsr;
 				end
 
-				if(rw_wait) begin
-					next_regs = regs;
-					cur_reg = prev_reg;
-					raddr = prev_raddr;
+				offset = prev_offset + 6'h4;
+				offset_sel = insn[24] ? offset : prev_offset;
+				raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+				if(insn[20]) begin
+					next_write_reg = !rw_wait;
+					next_write_num = cur_reg;
+					next_write_data = rd_data;
 				end
-				else begin
-					offset = prev_offset + 6'h4;
-					offset_sel = insn[24] ? offset : prev_offset;
-					raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
-					if(insn[20]) begin
-						next_write_reg = 1'b1;
-						next_write_num = cur_reg;
-						next_write_data = rd_data;
-					end
+				if (rw_wait) begin
+					next_regs = regs;
+					cur_reg = prev_reg;	/* whoops, do this one again */
 				end
 
 				st_read = cur_reg;
 				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
 				busaddr = raddr;
 				
-				$display("LDMSTM: Stage 2: Writing: reg %d, wr_data %08x, addr %08x", cur_reg, wr_data, busaddr);
+				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
 
 				outstall = 1'b1;
 
@@ -376,9 +384,11 @@ module Memory(
 				next_write_num = insn[19:16];
 				next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
 				next_lsm_state = 3'b001;
+				$display("LDMSTM: Stage 3: Writing back");
 			end
-			default: begin end
+			default: $stop;
 			endcase
+			$display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
 		end
 		`DECODE_LDCSTC: if(!inbubble) begin
 			$display("WARNING: Unimplemented LDCSTC");
@@ -418,5 +428,8 @@ module Memory(
 		end
 		default: begin end
 		endcase
+		
+		if ((flush || delayedflush) && !outstall)
+			next_outbubble = 1'b1;
 	end
 endmodule