X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/b3bb2fb8d24456b2683c5bdb8b3b195d0f600a97..b455d4811bb209ccddf70e8789a9efcb92536121:/Memory.v?ds=sidebyside

diff --git a/Memory.v b/Memory.v
index 2b4b2a4..e10a2e7 100644
--- a/Memory.v
+++ b/Memory.v
@@ -3,10 +3,6 @@
 module Memory(
 	input clk,
 	input Nrst,
-	input [31:0] pc,
-	input [31:0] insn,
-	input [31:0] base,
-	input [31:0] offset,
 
 	/* bus interface */
 	output reg [31:0] busaddr,
@@ -19,27 +15,54 @@ module Memory(
 	/* regfile interface */
 	output reg [3:0] st_read,
 	input [31:0] st_data,
+	
+	/* stage inputs */
+	input inbubble,
+	input [31:0] pc,
+	input [31:0] insn,
+	input [31:0] op0,
+	input [31:0] op1,
+	input [31:0] op2,
+	input write_reg,
+	input [3:0] write_num,
+	input [31:0] write_data,
 
-	/* writeback to base */
-	output reg writeback,
-	output reg [3:0] regsel,
-	output reg [31:0] regdata,
-
-	/* pc stuff */
-	output reg [31:0] outpc,
-	output reg [31:0] newpc,
-
-	/* stall */
-	output outstall,
+	/* outputs */
+	output reg outstall,
 	output reg outbubble,
-	output reg flush
-);
+	output reg [31:0] outpc,
+	output reg [31:0] outinsn,
+	output reg out_write_reg = 1'b0,
+	output reg [3:0] out_write_num = 4'bxxxx,
+	output reg [31:0] out_write_data = 32'hxxxxxxxx
+	);
 
 	reg [31:0] addr, raddr;
+	reg next_notdone, next_inc_next;
+	reg [31:0] align_s1, align_s2, align_rddata;
+
+	wire next_outbubble;	
+	wire next_write_reg;
+	wire [3:0] next_write_num;
+	wire [31:0] next_write_data;
+
+	reg [15:0] regs, next_regs;
+
 	reg notdone = 1'b0;
 	reg inc_next = 1'b0;
-	wire [31:0] align_s1, align_s2, align_rddata;
-	assign outstall = rw_wait | notdone;
+
+	always @(posedge clk)
+	begin
+		outpc <= pc;
+		outinsn <= insn;
+		outbubble <= next_outbubble;
+		out_write_reg <= next_write_reg;
+		out_write_num <= next_write_num;
+		out_write_data <= next_write_data;
+		notdone <= next_notdone;
+		inc_next <= next_inc_next;
+		regs <= next_regs;
+	end
 
 	always @(*)
 	begin
@@ -50,76 +73,94 @@ module Memory(
 		wr_data = 32'hxxxxxxxx;
 		busaddr = 32'hxxxxxxxx;
 		outstall = 1'b0;
+		next_notdone = 1'b0;
+		next_write_reg = write_reg;
+		next_write_num = write_num;
+		next_write_data = write_data;
+		next_inc_next = 1'b0;
+		next_outbubble = inbubble;
+		outstall = 1'b0;
+		
 		casez(insn)
 		`DECODE_LDRSTR_UNDEFINED: begin end
 		`DECODE_LDRSTR: begin
-			addr = insn[23] ? base + offset : base - offset; /* up/down select */
-			raddr = insn[24] ? base : addr;
-			busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
-			rd_req = insn[20];
-			wr_req = ~insn[20];
-			if(!insn[20]) begin /* store */
-				st_read = insn[15:12];
-				wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
-			end
-			else if(insn[15:12] == 4'hF)
-				flush = 1'b1;
-		end
-		`DECODE_LDMSTM: begin
-		end
-		default: begin end
-		endcase
-	end
-
-	assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-	assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-	assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
-	always @(posedge clk)
-	begin
-		outpc <= pc;
-		outbubble <= rw_wait;
-		casez(insn)
-		`DECODE_LDRSTR_UNDEFINED: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
-		`DECODE_LDRSTR: begin
-			if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
-				if(insn[15:12] == 4'hF) begin
-					newpc <= align_rddata;
+			if (!inbubble) begin
+				next_outbubble = rw_wait;
+				outstall = rw_wait | notdone;
+			
+				addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+				raddr = insn[24] ? op0 : addr; /* pre/post increment */
+				busaddr = {raddr[31:2], 2'b0};
+				rd_req = insn[20];
+				wr_req = ~insn[20];
+				
+				/* rotate to correct position */
+				align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+				align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+				/* select byte or word */
+				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+				
+				if(!insn[20]) begin
+					wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+				end
+				else if(!inc_next) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[15:12];
+					next_write_data = align_rddata;
+					next_inc_next = 1'b1;
 				end
-				else begin
-					writeback <= 1'b1;
-					regsel <= insn[15:12];
-					regdata <= align_rddata;
+				else if(insn[21]) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[19:16];
+					next_write_data = addr;
 				end
-				inc_next <= 1'b1;
-			end
-			else if(insn[21]) begin /* write back */
-				writeback <= 1'b1;
-				regsel <= insn[19:16];
-				regdata <= addr;
-				inc_next <= 1'b0;
-			end else begin
-				writeback <= 1'b0;
-				inc_next <= 1'b0;
-				regsel <= 4'hx;
-				regdata <= 32'hxxxxxxxx;
-			end
-			notdone <= rw_wait & insn[20] & insn[21];
+				next_notdone = rw_wait & insn[20] & insn[21];
+			end
 		end
 		`DECODE_LDMSTM: begin
+			busaddr = {op0[31:2], 2'b0};
+			rd_req = insn[20];
+			wr_req = ~insn[20];
+			casez(regs)
+			16'b???????????????1: begin
+				next_regs = regs;
+			end
+			16'b??????????????10: begin
+			end
+			16'b?????????????100: begin
+			end
+			16'b????????????1000: begin
+			end
+			16'b???????????10000: begin
+			end
+			16'b??????????100000: begin
+			end
+			16'b?????????1000000: begin
+			end
+			16'b????????10000000: begin
+			end
+			16'b???????100000000: begin
+			end
+			16'b??????1000000000: begin
+			end
+			16'b?????10000000000: begin
+			end
+			16'b????100000000000: begin
+			end
+			16'b???1000000000000: begin
+			end
+			16'b??10000000000000: begin
+			end
+			16'b?100000000000000: begin
+			end
+			16'b1000000000000000: begin
+			end
+			default: begin
+				next_inc_next = 1'b1;
+			end
+			endcase
 		end
-		default: begin
-			writeback <= 1'b0;
-			regsel <= 4'hx;
-			regdata <= 32'hxxxxxxxx;
-			notdone <= 1'b0;
-		end
+		default: begin end
 		endcase
 	end
-
 endmodule