X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/a7297aa515ea46bb06bd8b76d9c1edd059650c83..1e7ff543e49341fedea742d7b8b674111d852748:/RegFile.v

diff --git a/RegFile.v b/RegFile.v
index 836eae4..dec1907 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -7,8 +7,8 @@ module RegFile(
 	output wire [31:0] rf__rdata_1_1a,
 	input        [3:0] rf__read_2_1a,
 	output wire [31:0] rf__rdata_2_1a,
-	input        [3:0] rf__read_3_4a,
-	output wire [31:0] rf__rdata_3_4a,
+	input        [3:0] rf__read_3_3a,
+	output wire [31:0] rf__rdata_3_3a,
 	output wire [31:0] spsr,
 	input              write,
 	input        [3:0] write_reg,
@@ -26,7 +26,7 @@ module RegFile(
 	assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a];
 	assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a];
 	assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a];
-	assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a];
+	assign rf__rdata_3_3a = ((rf__read_3_3a == write_reg) && write) ? write_data : regfile[rf__read_3_3a];
 	assign spsr = regfile[4'hF];
 	
 	always @(posedge clk or negedge Nrst)