X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/9a0d0e43d3ed0fc332924698603c7146f8903d95..778ef14fd7c4dadb9923bb9b8628843587a43e1c:/Memory.v

diff --git a/Memory.v b/Memory.v
index c9d080d..33bd674 100644
--- a/Memory.v
+++ b/Memory.v
@@ -11,11 +11,20 @@ module Memory(
 	input rw_wait,
 	output reg [31:0] wr_data,
 	input [31:0] rd_data,
+	output reg [2:0] data_size;
 
 	/* regfile interface */
 	output reg [3:0] st_read,
 	input [31:0] st_data,
 	
+	/* Coprocessor interface */
+	output reg cp_req,
+	input cp_ack,
+	input cp_busy,
+	output cp_rnw,	/* 1 = read from CP, 0 = write to CP */
+	input [31:0] cp_read,
+	output reg [31:0] cp_write,
+	
 	/* stage inputs */
 	input inbubble,
 	input [31:0] pc,
@@ -42,9 +51,9 @@ module Memory(
 	);
 
 	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
+	reg [31:0] prevaddr;
 	reg [3:0] next_regsel, cur_reg, prev_reg;
 	reg next_writeback;
-	reg [31:0] align_s1, align_s2, align_rddata;
 
 	wire next_outbubble;	
 	wire next_write_reg;
@@ -52,6 +61,12 @@ module Memory(
 	wire [31:0] next_write_data;
 
 	reg [1:0] lsr_state = 2'b01, next_lsr_state;
+	reg [31:0] align_s1, align_s2, align_rddata;
+
+	reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
+	reg [31:0] lsrh_rddata;
+	reg [15:0] lsrh_rddata_s1;
+	reg [7:0] lsrh_rddata_s2;
 
 	reg [15:0] regs, next_regs;
 	reg [2:0] lsm_state = 3'b001, next_lsm_state;
@@ -75,106 +90,166 @@ module Memory(
 		out_cpsr <= next_outcpsr;
 		out_spsr <= spsr;
 		swp_state <= next_swp_state;
+		lsm_state <= next_lsm_state;
+		lsr_state <= next_lsr_state;
+		lsrh_state <= next_lsrh_state;
+		prevaddr <= addr;
 	end
 
 	always @(*)
 	begin
-		addr = 32'hxxxxxxxx;
+		addr = prevaddr;
 		raddr = 32'hxxxxxxxx;
 		rd_req = 1'b0;
 		wr_req = 1'b0;
 		wr_data = 32'hxxxxxxxx;
 		busaddr = 32'hxxxxxxxx;
+		data_size = 3'bxxx;
 		outstall = 1'b0;
 		next_write_reg = write_reg;
 		next_write_num = write_num;
 		next_write_data = write_data;
 		next_outbubble = inbubble;
-		outstall = 1'b0;
 		next_regs = regs;
+		cp_req = 1'b0;
+		cp_rnw = 1'bx;
+		cp_write = 32'hxxxxxxxx;
 		offset = prev_offset;
 		next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+		lsrh_rddata = 32'hxxxxxxxx;
+		lsrh_rddata_s1 = 32'hxxxxxxxx;
+		lsrh_rddata_s2 = 32'hxxxxxxxx;
 		next_lsm_state = lsm_state;
 		next_lsr_state = lsr_state;
+		next_lsrh_state = lsrh_state;
 		next_swp_oldval = swp_oldval;
 		next_swp_state = swp_state;
 		cur_reg = prev_reg;
 
+		/* XXX shit not given about endianness */
 		casez(insn)
-		`DECODE_ALU_SWP: begin
-			if(!inbubble) begin
-				outstall = rw_wait;
-				next_outbubble = rw_wait;
-				busaddr = {op0[31:2], 2'b0};
-				case(swp_state)
-				2'b01: begin
-					rd_req = 1'b1;
-					outstall = 1'b1;
-					if(!rw_wait) begin
-						next_swp_state = 2'b10;
-						next_swp_oldval = rd_data;
-					end
+		`DECODE_ALU_SWP: if(!inbubble) begin
+			outstall = rw_wait;
+			next_outbubble = rw_wait;
+			busaddr = {op0[31:2], 2'b0};
+			data_size = insn[22] ? 3'b001 : 3'b100;
+			case(swp_state)
+			2'b01: begin
+				rd_req = 1'b1;
+				outstall = 1'b1;
+				if(!rw_wait) begin
+					next_swp_state = 2'b10;
+					next_swp_oldval = rd_data;
 				end
-				2'b10: begin
-					wr_req = 1'b1;
-					wr_data = op1;
+			end
+			2'b10: begin
+				wr_req = 1'b1;
+				wr_data = insn[22] ? {4{op1[7:0]}} : op1;
+				next_write_reg = 1'b1;
+				next_write_num = insn[15:12];
+				next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
+				if(!rw_wait)
+					next_swp_state = 2'b01;
+			end
+			default: begin end
+			endcase
+		end
+		`DECODE_ALU_HDATA_REG,
+		`DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+			next_outbubble = rw_wait;
+			outstall = rw_wait;
+			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+			raddr = insn[24] ? op0 : addr; /* pre/post increment */
+			busaddr = raddr;
+			/* rotate to correct position */
+			case(insn[6:5])
+			2'b00: begin end /* swp */
+			2'b01: begin /* unsigned half */
+				wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
+				data_size = 3'b010;
+				lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
+			end
+			2'b10: begin /* signed byte */
+				wr_data = {4{op2[7:0]}};
+				data_size = 3'b001;
+				lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
+				lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+				lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+			end
+			2'b11: begin /* signed half */
+				wr_data = {2{op2[15:0]}};
+				data_size = 3'b010;
+				lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
+			end
+			endcase
+
+			case(lsrh_state)
+			2'b01: begin
+				rd_req = insn[20];
+				wr_req = ~insn[20];
+				next_write_num = insn[15:12];
+				next_write_data = lsrh_rddata;
+				if(insn[20]) begin
 					next_write_reg = 1'b1;
-					next_write_num = insn[15:12];
-					next_write_data = swp_oldval;
+				end
+				if(insn[21] | !insn[24]) begin
+					outstall = 1'b1;
 					if(!rw_wait)
-						next_swp_state = 2'b01;
+						next_lsrh_state = 2'b10;
 				end
-				default: begin end
-				endcase
 			end
+			2'b10: begin
+				next_write_reg = 1'b1;
+				next_write_num = insn[19:16];
+				next_write_data = addr;
+				next_lsrh_state = 2'b10;
+			end
+			default: begin end
+			endcase
 		end
 		`DECODE_LDRSTR_UNDEFINED: begin end
-		`DECODE_LDRSTR: begin
-			if (!inbubble) begin
-				next_outbubble = rw_wait;
-				outstall = rw_wait;
-				addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
-				raddr = insn[24] ? op0 : addr; /* pre/post increment */
-				busaddr = {raddr[31:2], 2'b0};
-
-				/* rotate to correct position */
-				align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-				align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-				/* select byte or word */
-				align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-				if(!insn[20]) begin
-					wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
-				end
-				case(lsr_state)
-				2'b01: begin
-					rd_req = insn[20];
-					wr_req = ~insn[20];
-
-					if(insn[20]) begin
-						next_write_reg = 1'b1;
-						next_write_num = insn[15:12];
-						next_write_data = align_rddata;
-					end
-
-					if(insn[21]) begin
-						outstall = 1'b1;
-						if(!rw_wait)
-							next_lsr_state = 2'b10;
-					end
+		`DECODE_LDRSTR: if(!inbubble) begin
+			next_outbubble = rw_wait;
+			outstall = rw_wait;
+			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+			raddr = insn[24] ? op0 : addr; /* pre/post increment */
+			busaddr = raddr;
+			/* rotate to correct position */
+			align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+			align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+			/* select byte or word */
+			align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+			wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+			data_size = insn[22] ? 3'b001 : 3'b100;
+			case(lsr_state)
+			2'b01: begin
+				rd_req = insn[20];
+				wr_req = ~insn[20];
+				next_write_reg = 1'b1;
+				next_write_num = insn[15:12];
+				if(insn[20]) begin
+					next_write_data = align_rddata;
 				end
-				2'b10: begin
-					next_write_reg = 1'b1;
-					next_write_num = insn[19:16];
-					next_write_data = addr;
-					next_lsr_state = 2'b10;
+				if(insn[21] | !insn[24]) begin
+					outstall = 1'b1;
+					if(!rw_wait)
+						next_lsr_state = 2'b10;
 				end
-				default: begin end
-				endcase
 			end
+			2'b10: begin
+				next_write_reg = 1'b1;
+				next_write_num = insn[19:16];
+				next_write_data = addr;
+				next_lsr_state = 2'b10;
+			end
+			default: begin end
+			endcase
 		end
-		`DECODE_LDMSTM: begin
+		/* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+		`DECODE_LDMSTM: if(!inbubble) begin
 			outstall = rw_wait;
 			next_outbubble = rw_wait;
+			data_size = 3'b100;
 			case(lsm_state)
 			3'b001: begin
 //				next_regs = insn[23] ? op1[15:0] : op1[0:15];
@@ -281,7 +356,7 @@ module Memory(
 
 				st_read = cur_reg;
 				wr_data = st_data;
-				busaddr = {raddr[31:2], 2'b0};
+				busaddr = raddr;
 
 				outstall = 1'b1;
 
@@ -298,6 +373,42 @@ module Memory(
 			default: begin end
 			endcase
 		end
+		`DECODE_LDCSTC: if(!inbubble) begin
+			$display("WARNING: Unimplemented LDCSTC");
+		end
+		`DECODE_CDP: if(!inbubble) begin
+			cp_req = 1;
+			if (cp_busy) begin
+				outstall = 1;
+				next_outbubble = 1;
+			end
+			if (!cp_ack) begin
+				/* XXX undefined instruction trap */
+				$display("WARNING: Possible CDP undefined instruction");
+			end
+		end
+		`DECODE_MRCMCR: if(!inbubble) begin
+			cp_req = 1;
+			cp_rnw = insn[20] /* L */;
+			if (insn[20] == 0 /* store to coprocessor */)
+				cp_write = op0;
+			else begin
+				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[15:12];
+					next_write_data = cp_read;
+				end else
+					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
+			end
+			if (cp_busy) begin
+				outstall = 1;
+				next_outbubble = 1;
+			end
+			if (!cp_ack) begin
+				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
+			end
+			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
+		end
 		default: begin end
 		endcase
 	end