X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/981270c3e15a542f5ca03780c562bc24c6c90735..4dc317445bd5132ca57744d7faf27731ea10d3b9:/ICache.v

diff --git a/ICache.v b/ICache.v
index 2e28adf..d9fbf04 100644
--- a/ICache.v
+++ b/ICache.v
@@ -32,7 +32,7 @@ module ICache(
 	reg [21:0] cache_tags [15:0];
 	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
 	
-	reg [4:0] i;
+	integer i;
 	initial
 		for (i = 0; i < 16; i = i + 1)
 		begin
@@ -45,6 +45,8 @@ module ICache(
 	wire [3:0] rd_idx = rd_addr[9:6];
 	wire [21:0] rd_tag = rd_addr[31:10];
 	
+	reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
+	
 	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
 	
 	always @(*) begin	/* XXX does this work nowadays? */
@@ -63,16 +65,22 @@ module ICache(
 			bus_rd = 0;
 		end
 	
-	always @(posedge clk)
-		if (rd_req && !cache_hit) begin
-			if (bus_ready) begin	/* Started the fill, and we have data. */
-				$display("CACHE FILL: rq adr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+	always @(posedge clk) begin
+		prev_rd_addr <= {rd_addr[31:6], 6'b0};
+		if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+			cache_fill_pos <= 0;
+		else if (rd_req && !cache_hit) begin
+			if (bus_ack && bus_ready) begin	/* Started the fill, and we have data. */
+				$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
 				cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
 				cache_fill_pos <= cache_fill_pos + 1;
 				if (cache_fill_pos == 15) begin	/* Done? */
 					cache_tags[rd_idx] <= rd_tag;
 					cache_valid[rd_idx] <= 1;
-				end
+					$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
+				end else
+					cache_valid[rd_idx] <= 0;
 			end
 		end
+	end
 endmodule