X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/96f7e6e169cb1471891980770630f3bed700c604..8077f6bb8995fc352b652d81ead780b573079de2:/Decode.v?ds=inline diff --git a/Decode.v b/Decode.v index 6cfe08b..c63fd9d 100644 --- a/Decode.v +++ b/Decode.v @@ -2,13 +2,17 @@ module Decode( input clk, + input stall, input [31:0] insn, input [31:0] inpc, input [31:0] incpsr, + input [31:0] inspsr, output reg [31:0] op0, output reg [31:0] op1, output reg [31:0] op2, output reg carry, + output reg [31:0] outcpsr, + output reg [31:0] outspsr, output reg [3:0] read_0, output reg [3:0] read_1, @@ -61,11 +65,12 @@ module Decode( `DECODE_BRANCH, /* Branch */ `DECODE_LDCSTC, /* Coprocessor data transfer */ `DECODE_CDP, /* Coprocessor data op */ - `DECODE_MRCMCR, /* Coprocessor register transfer */ `DECODE_SWI: /* SWI */ - rpc = inpc - 8; + rpc = inpc + 8; + `DECODE_MRCMCR: /* Coprocessor register transfer */ + rpc = inpc + 12; `DECODE_ALU: /* ALU */ - rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8)); + rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8)); default: /* X everything else out */ rpc = 32'hxxxxxxxx; endcase @@ -135,16 +140,20 @@ module Decode( begin read_0 = insn[19:16]; read_1 = insn[3:0]; - + read_2 = insn[15:12]; + op0_out = regs0; op1_out = regs1; + op2_out = regs2; end `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */ begin read_0 = insn[19:16]; + read_1 = insn[15:12]; op0_out = regs0; op1_out = {24'b0, insn[11:8], insn[3:0]}; + op2_out = regs1; end `DECODE_ALU: /* ALU */ begin @@ -169,6 +178,7 @@ module Decode( begin read_0 = insn[19:16]; /* Rn */ read_1 = insn[3:0]; /* Rm */ + read_2 = insn[15:12]; op0_out = regs0; if(insn[25]) begin @@ -178,6 +188,7 @@ module Decode( op1_out = shift_res; carry_out = shift_cflag_out; end + op2_out = regs2; end `DECODE_LDMSTM: /* Block data transfer */ begin @@ -216,10 +227,15 @@ module Decode( always @ (posedge clk) begin - op0 <= op0_out; /* Rn - always */ - op1 <= op1_out; /* 'operand 2' - Rm */ - op2 <= op2_out; /* thirdedge - Rs */ - carry <= carry_out; + if (!stall) + begin + op0 <= op0_out; /* Rn - always */ + op1 <= op1_out; /* 'operand 2' - Rm */ + op2 <= op2_out; /* thirdedge - Rs */ + carry <= carry_out; + outcpsr <= incpsr; + outspsr <= inspsr; + end end endmodule