X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/932d2ed6999912bd7a85a3972a48109c127570f3..f61f8d6fb3090fa94005148aef02a219ad088da8:/Decode.v

diff --git a/Decode.v b/Decode.v
index cbe6184..d07b95a 100644
--- a/Decode.v
+++ b/Decode.v
@@ -10,17 +10,18 @@ module Decode(
 	output reg [31:0] op2,
 	output reg carry,
 
-	output [3:0] read_0,
-	output [3:0] read_1,
-	output [3:0] read_2,
+	output reg [3:0] read_0,
+	output reg [3:0] read_1,
+	output reg [3:0] read_2,
 	input [31:0] rdata_0,
 	input [31:0] rdata_1,
 	input [31:0] rdata_2
 	);
 
-	wire [31:0] regs0, regs1, regs2, rpc;
-	wire [31:0] op0_out, op1_out, op2_out;
-	wire carry_out;
+	wire [31:0] regs0, regs1, regs2;
+	reg [31:0] rpc;
+	reg [31:0] op0_out, op1_out, op2_out;
+	reg carry_out;
 
 	/* shifter stuff */
 	wire [31:0] shift_oper;
@@ -236,11 +237,12 @@ module IREALLYHATEARMSHIFT(
 	input [31:0] operand,
 	input [31:0] reg_amt,
 	input cflag_in,
-	output [31:0] res,
-	output cflag_out
+	output reg [31:0] res,
+	output reg cflag_out
 );
 	wire [5:0] shift_amt;
-	wire rshift_cout, is_arith, is_rot;
+	reg is_arith, is_rot;
+	wire rshift_cout;
 	wire [31:0] rshift_res;
 
 	assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
@@ -305,8 +307,8 @@ module SuckLessShifter(
 	input [5:0] amt,
 	input is_arith,
 	input is_rot,
-	output [31:0] res,
-	output carryout
+	output wire [31:0] res,
+	output wire carryout
 );
 
 	wire [32:0] stage1, stage2, stage3, stage4, stage5;
@@ -315,18 +317,18 @@ module SuckLessShifter(
 
 	/* do a barrel shift */
 	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
-	assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
-	assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
-	assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
-	assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
-	assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
+	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
+	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
+	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
+	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
+	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
 
 endmodule
 
 module SuckLessRotator(
 	input [31:0] oper,
 	input [3:0] amt,
-	output [31:0] res
+	output wire [31:0] res
 );
 
 	wire [31:0] stage1, stage2, stage3;