X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/90ff449a4ff253d31572db4bf6bdabe61b6b3783..03bbc40b28ecb9fab7f459f627d3843ba3f10b16:/BlockRAM.v diff --git a/BlockRAM.v b/BlockRAM.v index cfb5d70..e0eceeb 100644 --- a/BlockRAM.v +++ b/BlockRAM.v @@ -12,16 +12,14 @@ module BlockRAM( * 0x00004000. rdata and ready must be driven to zero if the * address is not within the range of this module. */ - wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000; - /* verilator lint_off WIDTH */ - wire [13:2] ramaddr = bus_addr & 32'h3FFC; /* mask off lower two bits + wire decode = bus_addr[31:14] == 18'b0; + wire [13:0] ramaddr = {bus_addr[13:2], 2'b0}; /* mask off lower two bits * for word alignment */ - /* verilator lint_on WIDTH */ - + reg [31:0] data [(16384 / 4 - 1):0]; reg [31:0] temprdata = 0; - reg [13:2] lastread = 0; + reg [13:0] lastread = 14'h3FFF; assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0; assign bus_ready = decode && @@ -33,11 +31,11 @@ module BlockRAM( always @(posedge clk) begin if (bus_wr && decode) - data[ramaddr] <= bus_wdata; + data[ramaddr[13:2]] = bus_wdata; /* This is not allowed to be conditional -- stupid Xilinx * blockram. */ - temprdata <= data[ramaddr]; + temprdata <= data[ramaddr[13:2]]; lastread <= ramaddr; end endmodule