X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/8744c23dbf6a3c38649c800ae3d96e7e465e01fb..1e7ff543e49341fedea742d7b8b674111d852748:/xst/Makefile

diff --git a/xst/Makefile b/xst/Makefile
index 074ec26..1c86905 100644
--- a/xst/Makefile
+++ b/xst/Makefile
@@ -1,6 +1,22 @@
 TARGET = FireARM
-VLOGS = Console.v  ARM_Constants.v  BigBlockRAM.v  BlockRAM.v  BusArbiter.v  DCache.v  Decode.v  Execute.v  Fetch.v  ICache.v  Issue.v  Memory.v  RegFile.v  system.v  Terminal.v  Writeback.v
-VLOGS_ALL = $(VLOGS) ram.hex
+VLOGS = Console.nexys2.v \
+        ../ARM_Constants.v \
+        ../BigBlockRAM.v \
+        ../BlockRAM.v \
+        ../CellularRAM.v \
+        ../BusArbiter.v \
+        ../DCache.v \
+        ../Decode.v \
+        ../Execute.v \
+        ../Fetch.v \
+        ../ICache.v \
+        ../Issue.v \
+        ../Memory.v \
+        ../RegFile.v \
+        ../system.v \
+        ../Terminal.v \
+        ../Writeback.v
+VLOGS_ALL = $(VLOGS) ram.hex ibmpc1.mem scancodes.unshifted.hex scancodes.shifted.hex
 
 all: fpga_target
 
@@ -26,7 +42,7 @@ BITGEN_OPTS = \
 	-g Match_cycle:2 \
 	-g DriveDone:No
 
-fpga_target: $(TARGET).bit
+fpga_target: $(TARGET).svf
 
 $(TARGET).ngc: $(TARGET).xst $(VLOGS_ALL)
 	@mkdir -p xst/projnav.tmp
@@ -56,10 +72,10 @@ sim/%.v: %.ngc
 	netgen -ofmt verilog -w -dir sim $<
 
 $(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf
-	ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc5vlx110t-ff1136-1 "$(TARGET).ngc" $(TARGET).ngd
+	ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc3s1200e-fg320-5 "$(TARGET).ngc" $(TARGET).ngd
 
 $(TARGET)_map.ncd: $(TARGET).ngd
-	map -w -p xc5vlx110t-ff1136-1 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf
+	map -w -p xc3s1200e-fg320-5 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf
 
 $(TARGET).ncd: $(TARGET)_map.ncd
 	par -w -ol std -t 1 $(TARGET)_map.ncd $(TARGET).ncd $(TARGET).pcf