X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/821617bbbb52327fbfc1a40f0dfb551c3ed8209a..69e8e27ffa6c1124ac91f55afe6d9a17d815a8b3:/RegFile.v

diff --git a/RegFile.v b/RegFile.v
index f5a63ae..c0e5abd 100644
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,13 +1,16 @@
 module RegFile(
 	input clk,
 	input [3:0] read_0,
-	output reg [31:0] rdata_0,
+	output wire [31:0] rdata_0,
 	input [3:0] read_1,
-	output reg [31:0] rdata_1,
+	output wire [31:0] rdata_1,
 	input [3:0] read_2,
-	output reg [31:0] rdata_2,
-	input [3:0] write,
-	input write_req,
+	output wire [31:0] rdata_2,
+	input [3:0] read_3,
+	output wire [31:0] rdata_3,
+	output wire [31:0] spsr,
+	input write,
+	input [3:0] write_reg,
 	input [31:0] write_data
 	);
 	
@@ -22,35 +25,23 @@ module RegFile(
 		regfile[4'h5] = 32'h00500000;
 		regfile[4'h6] = 32'h05000000;
 		regfile[4'h7] = 32'h50000000;
-		regfile[4'h8] = 32'h0000000A;
-		regfile[4'h9] = 32'h000000A0;
-		regfile[4'hA] = 32'h00000A00;
-		regfile[4'hB] = 32'h0000A000;
-		regfile[4'hC] = 32'h000A0000;
-		regfile[4'hD] = 32'h00A00000;
-		regfile[4'hE] = 32'h0A000000;
-		regfile[4'hF] = 32'hA0000000;
+		regfile[4'h8] = 32'hA0000000;
+		regfile[4'h9] = 32'h0A000000;
+		regfile[4'hA] = 32'h00A00000;
+		regfile[4'hB] = 32'h000A0000;
+		regfile[4'hC] = 32'h0000A000;
+		regfile[4'hD] = 32'h00000A00;
+		regfile[4'hE] = 32'h000000A0;
+		regfile[4'hF] = 32'h00000000;	/* Start off claiming we are in user mode. */
 	end
 	
-	always @(*)
-	begin
-		if ((read_0 == write) && write_req)
-			rdata_0 = write_data;
-		else
-			rdata_0 = regfile[read_0];
-		
-		if ((read_1 == write) && write_req)
-			rdata_1 = write_data;
-		else
-			rdata_1 = regfile[read_1];
-		
-		if ((read_2 == write) && write_req)
-			rdata_2 = write_data;
-		else
-			rdata_2 = regfile[read_2];
-	end
+	assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0];
+	assign rdata_1 = ((read_1 == write_reg) && write) ? write_data : regfile[read_1];
+	assign rdata_2 = ((read_2 == write_reg) && write) ? write_data : regfile[read_2];
+	assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3];
+	assign spsr = regfile[4'hF];
 	
 	always @(posedge clk)
-		if (write_req)
-			regfile[write] <= write_data;
+		if (write)
+			regfile[write_reg] <= write_data;
 endmodule