X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/7aa8541bb3a69361fcfe0e9b1148c693fd1043ec..1c2e57dc81bb31f2f577481bac788d279956dc39:/Issue.v diff --git a/Issue.v b/Issue.v index a450190..2df5bfa 100644 --- a/Issue.v +++ b/Issue.v @@ -2,7 +2,7 @@ module Issue( input clk, - input Nrst, + input Nrst, /* XXX not used yet */ input stall, /* pipeline control */ input flush, @@ -10,17 +10,16 @@ module Issue( input inbubble, /* stage inputs */ input [31:0] insn, input [31:0] inpc, + input [31:0] cpsr, - output reg outbubble, /* stage outputs */ - output reg [31:0] outpc - /* other */ + output reg outstall = 0, /* stage outputs */ + output reg outbubble = 1, + output reg [31:0] outpc = 0, + output reg [31:0] outinsn = 0 + /* XXX other? */ ); - always @(posedge clk) - begin - outbubble <= inbubble; - outpc <= inpc; - end + `ifdef COPY_PASTA_FODDER /* from page 2 of ARM7TDMIvE2.pdf */ @@ -230,4 +229,72 @@ module Issue( def_regs = 16'bxxxxxxxxxxxxxxxx; end endcase + + /* Condition checking logic */ + reg condition_met; + always @(*) + casez(insn[31:28]) + `COND_EQ: condition_met = cpsr[`CPSR_Z]; + `COND_NE: condition_met = !cpsr[`CPSR_Z]; + `COND_CS: condition_met = cpsr[`CPSR_C]; + `COND_CC: condition_met = !cpsr[`CPSR_C]; + `COND_MI: condition_met = cpsr[`CPSR_N]; + `COND_PL: condition_met = !cpsr[`CPSR_N]; + `COND_VS: condition_met = cpsr[`CPSR_V]; + `COND_VC: condition_met = !cpsr[`CPSR_V]; + `COND_HI: condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z]; + `COND_LS: condition_met = !cpsr[`CPSR_C] || cpsr[`CPSR_Z]; + `COND_GE: condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V]; + `COND_LT: condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V]; + `COND_GT: condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]); + `COND_LE: condition_met = cpsr[`CPSR_Z] || (cpsr[`CPSR_N] != cpsr[`CPSR_V]); + `COND_AL: condition_met = 1; + `COND_NV: condition_met = 0; + default: condition_met = 1'bx; + endcase + + /* Issue logic */ +`define STAGE_EXECUTE 0 +`define STAGE_MEMORY 1 +/* Once it's hit writeback, it's essentially hit the regfile so you're done. */ + reg cpsr_inflight [1:0]; + reg [15:0] regs_inflight [1:0]; + + reg waiting_cpsr; + reg waiting_regs; + wire waiting = waiting_cpsr | waiting_regs; + + initial + begin + cpsr_inflight[0] = 0; + cpsr_inflight[1] = 0; + regs_inflight[0] = 0; + regs_inflight[1] = 0; + end + + always @(*) + begin + waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); + waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); + + outstall = waiting && !inbubble; /* Happens in an always @*, because it is an exception. */ + end + + /* Actually do the issue. */ + always @(posedge clk) + begin + cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */ + cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr; + regs_inflight[0] <= regs_inflight[1]; + regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs; + + if (waiting) + begin + $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs); + end + + outbubble <= inbubble | waiting | !condition_met; + outpc <= inpc; + outinsn <= insn; + end endmodule