X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/666ceb038eeeb0125af3797e6cf76d0954b9431f..f05621b796e3d8f9036e2e5bbda5b7af1624b2e2:/Memory.v?ds=inline diff --git a/Memory.v b/Memory.v index eeec5a3..2e6ed0f 100644 --- a/Memory.v +++ b/Memory.v @@ -4,6 +4,8 @@ module Memory( input clk, input Nrst, + input flush, + /* bus interface */ output reg [31:0] busaddr, output reg rd_req, @@ -11,6 +13,7 @@ module Memory( input rw_wait, output reg [31:0] wr_data, input [31:0] rd_data, + output reg [2:0] data_size, /* regfile interface */ output reg [3:0] st_read, @@ -20,7 +23,7 @@ module Memory( output reg cp_req, input cp_ack, input cp_busy, - output cp_rnw, /* 1 = read from CP, 0 = write to CP */ + output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */ input [31:0] cp_read, output reg [31:0] cp_write, @@ -45,8 +48,8 @@ module Memory( output reg out_write_reg = 1'b0, output reg [3:0] out_write_num = 4'bxxxx, output reg [31:0] out_write_data = 32'hxxxxxxxx, - output reg [31:0] out_spsr = 32'hxxxxxxxx, - output reg [31:0] out_cpsr = 32'hxxxxxxxx + output reg [31:0] outspsr = 32'hxxxxxxxx, + output reg [31:0] outcpsr = 32'hxxxxxxxx ); reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr; @@ -54,10 +57,10 @@ module Memory( reg [3:0] next_regsel, cur_reg, prev_reg; reg next_writeback; - wire next_outbubble; - wire next_write_reg; - wire [3:0] next_write_num; - wire [31:0] next_write_data; + reg next_outbubble; + reg next_write_reg; + reg [3:0] next_write_num; + reg [31:0] next_write_data; reg [1:0] lsr_state = 2'b01, next_lsr_state; reg [31:0] align_s1, align_s2, align_rddata; @@ -84,16 +87,24 @@ module Memory( out_write_data <= next_write_data; regs <= next_regs; prev_reg <= cur_reg; - prev_offset <= offset; + if (!rw_wait) + prev_offset <= offset; prev_raddr <= raddr; - out_cpsr <= next_outcpsr; - out_spsr <= spsr; + outcpsr <= next_outcpsr; + outspsr <= spsr; swp_state <= next_swp_state; lsm_state <= next_lsm_state; lsr_state <= next_lsr_state; lsrh_state <= next_lsrh_state; prevaddr <= addr; end + + reg delayedflush = 0; + always @(posedge clk) + if (flush && outstall /* halp! I can't do it now, maybe later? */) + delayedflush <= 1; + else if (!outstall /* anything has been handled this time around */) + delayedflush <= 0; always @(*) begin @@ -103,19 +114,21 @@ module Memory( wr_req = 1'b0; wr_data = 32'hxxxxxxxx; busaddr = 32'hxxxxxxxx; + data_size = 3'bxxx; outstall = 1'b0; next_write_reg = write_reg; next_write_num = write_num; next_write_data = write_data; next_outbubble = inbubble; - outstall = 1'b0; next_regs = regs; cp_req = 1'b0; cp_rnw = 1'bx; cp_write = 32'hxxxxxxxx; offset = prev_offset; - next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr; + next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr; lsrh_rddata = 32'hxxxxxxxx; + lsrh_rddata_s1 = 16'hxxxx; + lsrh_rddata_s2 = 8'hxx; next_lsm_state = lsm_state; next_lsr_state = lsr_state; next_lsrh_state = lsrh_state; @@ -124,12 +137,12 @@ module Memory( cur_reg = prev_reg; /* XXX shit not given about endianness */ - /* TODO ldrh/strh */ casez(insn) `DECODE_ALU_SWP: if(!inbubble) begin outstall = rw_wait; next_outbubble = rw_wait; busaddr = {op0[31:2], 2'b0}; + data_size = insn[22] ? 3'b001 : 3'b100; case(swp_state) 2'b01: begin rd_req = 1'b1; @@ -141,10 +154,10 @@ module Memory( end 2'b10: begin wr_req = 1'b1; - wr_data = op1; + wr_data = insn[22] ? {4{op1[7:0]}} : op1; next_write_reg = 1'b1; next_write_num = insn[15:12]; - next_write_data = swp_oldval; + next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval; if(!rw_wait) next_swp_state = 2'b01; end @@ -163,16 +176,19 @@ module Memory( 2'b00: begin end /* swp */ 2'b01: begin /* unsigned half */ wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */ + data_size = 3'b010; lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]}; end 2'b10: begin /* signed byte */ wr_data = {4{op2[7:0]}}; + data_size = 3'b001; lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0]; lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0]; lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2}; end 2'b11: begin /* signed half */ wr_data = {2{op2[15:0]}}; + data_size = 3'b010; lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]}; end endcase @@ -206,7 +222,7 @@ module Memory( next_outbubble = rw_wait; outstall = rw_wait; addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */ - raddr = insn[24] ? op0 : addr; /* pre/post increment */ + raddr = insn[24] ? addr : op0; /* pre/post increment */ busaddr = raddr; /* rotate to correct position */ align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data; @@ -214,6 +230,7 @@ module Memory( /* select byte or word */ align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2; wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */ + data_size = insn[22] ? 3'b001 : 3'b100; case(lsr_state) 2'b01: begin rd_req = insn[20]; @@ -228,12 +245,13 @@ module Memory( if(!rw_wait) next_lsr_state = 2'b10; end + $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait); end 2'b10: begin next_write_reg = 1'b1; next_write_num = insn[19:16]; next_write_data = addr; - next_lsr_state = 2'b10; + next_lsr_state = 2'b01; end default: begin end endcase @@ -242,12 +260,14 @@ module Memory( `DECODE_LDMSTM: if(!inbubble) begin outstall = rw_wait; next_outbubble = rw_wait; + data_size = 3'b100; case(lsm_state) 3'b001: begin // next_regs = insn[23] ? op1[15:0] : op1[0:15]; /** verilator can suck my dick */ - next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7], - op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]}; + $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]); + next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7], + op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]}; offset = 6'b0; outstall = 1'b1; next_lsm_state = 3'b010; @@ -325,30 +345,29 @@ module Memory( next_regs = 16'b0; end endcase - cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg; + cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg; if(cur_reg == 4'hF && insn[22]) begin next_outcpsr = spsr; end - if(rw_wait) begin - next_regs = regs; - cur_reg = prev_reg; - raddr = prev_raddr; + offset = prev_offset + 6'h4; + offset_sel = insn[24] ? offset : prev_offset; + raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel}; + if(insn[20]) begin + next_write_reg = !rw_wait; + next_write_num = cur_reg; + next_write_data = rd_data; end - else begin - offset = prev_offset + 6'h4; - offset_sel = insn[24] ? offset : prev_offset; - raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel}; - if(insn[20]) begin - next_write_reg = 1'b1; - next_write_num = cur_reg; - next_write_data = rd_data; - end + if (rw_wait) begin + next_regs = regs; + cur_reg = prev_reg; /* whoops, do this one again */ end st_read = cur_reg; - wr_data = st_data; + wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data; busaddr = raddr; + + $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr); outstall = 1'b1; @@ -357,13 +376,15 @@ module Memory( end end 3'b100: begin - next_write_reg = 1'b1; + next_write_reg = insn[21] /* writeback */; next_write_num = insn[19:16]; next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset}; next_lsm_state = 3'b001; + $display("LDMSTM: Stage 3: Writing back"); end - default: begin end + default: $stop; endcase + $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall); end `DECODE_LDCSTC: if(!inbubble) begin $display("WARNING: Unimplemented LDCSTC"); @@ -397,10 +418,14 @@ module Memory( next_outbubble = 1; end if (!cp_ack) begin - $display("WARNING: Possible MRCMCR undefined instruction"); + $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy); end + $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy); end default: begin end endcase + + if ((flush || delayedflush) && !outstall) + next_outbubble = 1'b1; end endmodule