X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/60c7a4529713ba7f2f9ced57ed74ee9b65c9a233..d64d6ef9fffab25e5fffa4263e9ceb6ff85267da:/DCache.v?ds=inline

diff --git a/DCache.v b/DCache.v
index 098d9e8..356debc 100644
--- a/DCache.v
+++ b/DCache.v
@@ -51,7 +51,7 @@ module DCache(
 	always @(*) begin
 		rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
 		rd_data = cache_data[idx][didx_word];
-		if (!rw_wait)
+		if (!rw_wait && rd_req)
 			$display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
 	end
 	
@@ -67,7 +67,7 @@ module DCache(
 			bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
 			bus_rd = 1;
 		end else if (wr_req && bus_ack) begin
-			$display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", addr, wr_data);
+			$display("DCACHE: WRITE REQUEST: Addr %08x, data %08x, wait %d", addr, wr_data, rw_wait);
 			bus_addr = addr;
 			bus_wr = 1;
 			bus_wdata = wr_data;
@@ -79,13 +79,15 @@ module DCache(
 		if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
 		else if (rd_req && !cache_hit) begin
-			if (bus_ready) begin	/* Started the fill, and we have data. */
+			if (bus_ready && bus_ack) begin	/* Started the fill, and we have data. */
+				$display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
 				cache_data[idx][cache_fill_pos] <= bus_rdata;
 				cache_fill_pos <= cache_fill_pos + 1;
 				if (cache_fill_pos == 15) begin	/* Done? */
 					cache_tags[idx] <= tag;
 					cache_valid[idx] <= 1;
-				end
+				end else
+					cache_valid[idx] <= 0;
 			end
 		end else if (wr_req && cache_hit)
 			cache_data[idx][addr[5:2]] = wr_data;