X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/5ca2794992bb38cc521e32c47fba9135a2e2fbd5..bc572c5f98879e906b7dd10d67a799ffcf0524bb:/system.v diff --git a/system.v b/system.v index 251b43c..a52217c 100644 --- a/system.v +++ b/system.v @@ -34,13 +34,16 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp wire [31:0] icache_rd_data; wire stall_cause_issue; + wire stall_cause_execute; - wire stall_in_fetch = stall_cause_issue; - wire stall_in_issue = 0; - - wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr; + wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2; + wire decode_out_carry; wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2; wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2; + wire execute_out_stall, execute_out_bubble; + wire execute_out_write_reg; + wire [3:0] execute_out_write_num; + wire [31:0] execute_out_write_data; wire bubble_out_fetch; wire bubble_out_issue; @@ -76,14 +79,14 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp .Nrst(1 /* XXX */), .rd_addr(icache_rd_addr), .rd_req(icache_rd_req), .rd_wait(icache_rd_wait), .rd_data(icache_rd_data), - .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */), + .stall(stall_cause_issue), .jmp(0 /* XXX */), .jmppc(0 /* XXX */), .bubble(bubble_out_fetch), .insn(insn_out_fetch), .pc(pc_out_fetch)); Issue issue( .clk(clk), .Nrst(1 /* XXX */), - .stall(stall_in_issue), .flush(0 /* XXX */), + .stall(stall_cause_execute), .flush(0 /* XXX */), .inbubble(bubble_out_fetch), .insn(insn_out_fetch), .inpc(pc_out_fetch), .cpsr(0 /* XXX */), .outstall(stall_cause_issue), .outbubble(bubble_out_issue), @@ -99,10 +102,20 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp .clk(clk), .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */), .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2), - .outcpsr(decode_out_cpsr), + .carry(decode_out_carry), .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2)); + Execute execute( + .clk(clk), .Nrst(0), + .stall(0 /* XXX */), .flush(0 /* XXX */), + .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue), + .cpsr(0 /* XXX */), .op0(decode_out_op0), .op1(decode_out_op1), + .op2(decode_out_op2), .carry(decode_out_carry), + .outstall(stall_cause_execute), .outbubble(execute_out_bubble), + .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), + .write_data(execute_out_write_data)); + reg [31:0] clockno = 0; always @(posedge clk) begin @@ -110,6 +123,6 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp $display("------------------------------------------------------------------------------"); $display("%3d: FETCH: Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch); $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue); - $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, cpsr %08x", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr); + $display("%3d: DECODE: op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry); end endmodule