X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/5989b2f5fea99c05785a516ed029920fd2951112..332a17e70fa31a58205f06c237c72bb02ab90f7c:/Memory.v

diff --git a/Memory.v b/Memory.v
index c735ed9..eb0f69f 100644
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
 	input clk,
 	input Nrst,
 
+	input flush,
+
 	/* bus interface */
 	output reg [31:0] busaddr,
 	output reg rd_req,
@@ -45,8 +47,8 @@ module Memory(
 	output reg out_write_reg = 1'b0,
 	output reg [3:0] out_write_num = 4'bxxxx,
 	output reg [31:0] out_write_data = 32'hxxxxxxxx,
-	output reg [31:0] out_spsr = 32'hxxxxxxxx,
-	output reg [31:0] out_cpsr = 32'hxxxxxxxx
+	output reg [31:0] outspsr = 32'hxxxxxxxx,
+	output reg [31:0] outcpsr = 32'hxxxxxxxx
 	);
 
 	reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
@@ -80,8 +82,8 @@ module Memory(
 		prev_reg <= cur_reg;
 		prev_offset <= offset;
 		prev_raddr <= raddr;
-		out_cpsr <= next_outcpsr;
-		out_spsr <= spsr;
+		outcpsr <= next_outcpsr;
+		outspsr <= spsr;
 		swp_state <= next_swp_state;
 	end
 
@@ -104,7 +106,7 @@ module Memory(
 		cp_rnw = 1'bx;
 		cp_write = 32'hxxxxxxxx;
 		offset = prev_offset;
-		next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+		next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
 		next_lsm_state = lsm_state;
 		next_lsr_state = lsr_state;
 		next_swp_oldval = swp_oldval;
@@ -113,7 +115,9 @@ module Memory(
 
 		/* XXX shit not given about endianness */
 		/* TODO ldrh/strh */
-		casez(insn)
+		if (flush)
+			next_outbubble = 1'b1;
+		else casez(insn)
 		`DECODE_ALU_SWP: if(!inbubble) begin
 			outstall = rw_wait;
 			next_outbubble = rw_wait;
@@ -325,17 +329,21 @@ module Memory(
 			if (insn[20] == 0 /* store to coprocessor */)
 				cp_write = op0;
 			else begin
-				next_write_reg = 1'b1;
-				next_write_num = insn[15:12];
-				next_write_data = cp_read;
+				if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+					next_write_reg = 1'b1;
+					next_write_num = insn[15:12];
+					next_write_data = cp_read;
+				end else
+					next_outcpsr = {cp_read[31:28], cpsr[27:0]};
 			end
 			if (cp_busy) begin
 				outstall = 1;
 				next_outbubble = 1;
 			end
 			if (!cp_ack) begin
-				$display("WARNING: Possible MRCMCR undefined instruction");
+				$display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
 			end
+			$display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
 		end
 		default: begin end
 		endcase