X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/50d1792cc6f6958c314ee3470e986ddaa4e153a5..e92804b313459de4a6fc444975a0537a3fba17ad:/Memory.v

diff --git a/Memory.v b/Memory.v
index 947a7ad..3c7ec97 100644
--- a/Memory.v
+++ b/Memory.v
@@ -109,8 +109,6 @@ module Memory(
 		out_write_reg <= next_write_reg;
 		out_write_num <= next_write_num;
 		out_write_data <= next_write_data;
-		regs <= next_regs;
-		prev_reg <= cur_reg;
 		if (!rw_wait)
 			prev_offset <= offset;
 		prev_raddr <= raddr;
@@ -260,7 +258,7 @@ module Memory(
 					next_lsm_state = `LSM_BASEWB;
 				end
 				
-				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
+				$display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, st_data, busaddr);
 			end
 			`LSM_BASEWB: begin
 				outstall = 1;
@@ -482,7 +480,6 @@ module Memory(
 			2'b11: /* signed half */
 				data_size = 3'b010;
 			default: begin
-				wr_data = 32'hxxxxxxxx;
 				data_size = 3'bxxx;
 			end
 			endcase
@@ -502,7 +499,6 @@ module Memory(
 			addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 			raddr = insn[24] ? addr : op0; /* pre/post increment */
 			busaddr = raddr;
-			wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
 			data_size = insn[22] ? 3'b001 : 3'b100;
 			case (lsr_state)
 			`LSR_MEMIO: begin
@@ -574,7 +570,7 @@ module Memory(
 				endcase
 		end
 		`DECODE_LDMSTM: if (!inbubble)
-			if (lsr_state == `LSM_MEMIO)
+			if (lsm_state == `LSM_MEMIO)
 				wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
 		`DECODE_LDCSTC: begin end
 		`DECODE_CDP: begin end
@@ -584,8 +580,16 @@ module Memory(
 	end
 	
 	/* LDM/STM register control logic. */
+	always @(posedge clk)
+		if (!rw_wait || lsm_state != `LSM_MEMIO)
+		begin
+			prev_reg <= cur_reg;
+			regs <= next_regs;
+		end
+	
 	always @(*)
 	begin
+		st_read = 4'hx;
 		offset = prev_offset;
 		cur_reg = prev_reg;
 		next_regs = regs;
@@ -669,11 +673,6 @@ module Memory(
 				endcase
 				cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
 				
-				if (rw_wait) begin
-					next_regs = regs;
-					cur_reg = prev_reg;	/* whoops, do this one again */
-				end
-				
 				st_read = cur_reg;
 			end
 			`LSM_BASEWB: begin end
@@ -686,7 +685,6 @@ module Memory(
 	
 	always @(*)
 	begin
-		st_read = 4'hx;
 		do_rd_data_latch = 0;
 		
 		next_outbubble = inbubble;