X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/4ddc4b728c3d77fc388140a549afe636d527cfbd..dfddccfb552a24c60589696269a5325ec267c46d:/Issue.v

diff --git a/Issue.v b/Issue.v
index c3e5791..153f25f 100644
--- a/Issue.v
+++ b/Issue.v
@@ -12,7 +12,7 @@ module Issue(
 	input [31:0] inpc,
 	input [31:0] cpsr,
 	
-	output reg outstall = 0,	/* stage outputs */
+	output wire outstall,	/* stage outputs */
 	output reg outbubble = 1,
 	output reg [31:0] outpc = 0,
 	output reg [31:0] outinsn = 0
@@ -167,7 +167,7 @@ module Issue(
 						(idxbit(rs) | idxbit(rm)) :
 						(idxbit(rm)))) |
 				(((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
-			def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
+			def_cpsr = insn[20] /* S */;
 			def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
 		end
 		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
@@ -180,7 +180,7 @@ module Issue(
 		`DECODE_LDRSTR:
 		begin
 			use_cpsr = `COND_MATTERS(cond);
-			use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+			use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));
 			def_cpsr = 0;
 			def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
 		end
@@ -196,7 +196,7 @@ module Issue(
 			use_cpsr = `COND_MATTERS(cond);
 			use_regs = 0;
 			def_cpsr = 0;
-			def_regs = 0;
+			def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0;
 		end
 		`DECODE_LDCSTC:	/* Coprocessor data transfer */
 		begin
@@ -265,10 +265,6 @@ module Issue(
 	reg cpsr_inflight [1:0];
 	reg [15:0] regs_inflight [1:0];
 	
-	reg waiting_cpsr;
-	reg waiting_regs;
-	wire waiting = waiting_cpsr | waiting_regs;
-	
 	initial
 	begin
 		cpsr_inflight[0] = 0;
@@ -276,21 +272,25 @@ module Issue(
 		regs_inflight[0] = 0;
 		regs_inflight[1] = 0;
 	end
-		
-	always @(*)
-	begin
-		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
-		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
-		
-		outstall = (waiting && !inbubble) || stall;	/* Happens in an always @*, because it is an exception. */
-	end
 	
+	wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
+	wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+	wire waiting = waiting_cpsr | waiting_regs;
+	assign outstall = (waiting && !inbubble && !flush) || stall;
+
+	reg delayedflush = 0;
+	always @(posedge clk)
+		if (flush && outstall /* halp! I can't do it now, maybe later? */)
+			delayedflush <= 1;
+		else if (!outstall /* anything has been handled this time around */)
+			delayedflush <= 0;
+
 	/* Actually do the issue. */
 	always @(posedge clk)
 	begin
 		if (waiting)
 			$display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
-	
+
 		if (!stall)
 		begin
 			cpsr_inflight[0] <= cpsr_inflight[1];	/* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
@@ -298,7 +298,7 @@ module Issue(
 			regs_inflight[0] <= regs_inflight[1];
 			regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
 			
-			outbubble <= inbubble | waiting | !condition_met;
+			outbubble <= inbubble | waiting | !condition_met | flush | delayedflush;
 			outpc <= inpc;
 			outinsn <= insn;
 		end