X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/4dc317445bd5132ca57744d7faf27731ea10d3b9..8744c23dbf6a3c38649c800ae3d96e7e465e01fb:/ICache.v?ds=sidebyside

diff --git a/ICache.v b/ICache.v
index d9fbf04..8b9eac3 100644
--- a/ICache.v
+++ b/ICache.v
@@ -30,7 +30,7 @@ module ICache(
 	
 	reg cache_valid [15:0];
 	reg [21:0] cache_tags [15:0];
-	reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
+	reg [31:0] cache_data [255:0 /* {line, word} */];	//synthesis attribute ram_style of cache_data is distributed
 	
 	integer i;
 	initial
@@ -49,11 +49,6 @@ module ICache(
 	
 	wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
 	
-	always @(*) begin	/* XXX does this work nowadays? */
-		rd_wait = rd_req && !cache_hit;
-		rd_data = cache_data[rd_idx][rd_didx_word];
-	end
-	
 	reg [3:0] cache_fill_pos = 0;
 	assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
 	always @(*)
@@ -64,23 +59,27 @@ module ICache(
 			bus_addr = 0;
 			bus_rd = 0;
 		end
+
+	wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}];
+	always @(*) begin
+		rd_wait = rd_req && !cache_hit;
+		rd_data = curdata;
+	end
 	
 	always @(posedge clk) begin
 		prev_rd_addr <= {rd_addr[31:6], 6'b0};
 		if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))	/* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
 			cache_fill_pos <= 0;
-		else if (rd_req && !cache_hit) begin
-			if (bus_ack && bus_ready) begin	/* Started the fill, and we have data. */
-				$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
-				cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
-				cache_fill_pos <= cache_fill_pos + 1;
-				if (cache_fill_pos == 15) begin	/* Done? */
-					cache_tags[rd_idx] <= rd_tag;
-					cache_valid[rd_idx] <= 1;
-					$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
-				end else
-					cache_valid[rd_idx] <= 0;
-			end
+		else if (rd_req && !cache_hit && bus_ack && bus_ready) begin
+			$display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+			cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata;
+			cache_fill_pos <= cache_fill_pos + 1;
+			if (cache_fill_pos == 15) begin	/* Done? */
+				cache_tags[rd_idx] <= rd_tag;
+				cache_valid[rd_idx] <= 1;
+				$display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
+			end else
+				cache_valid[rd_idx] <= 0;
 		end
 	end
 endmodule