X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/48775efdc0074dd9a772e37ae43adf58b5c9be8c..2bdf3bcc2053a54580b37094edb73a47083118c9:/Fetch.v?ds=sidebyside

diff --git a/Fetch.v b/Fetch.v
index 7dd4bb0..3f28453 100644
--- a/Fetch.v
+++ b/Fetch.v
@@ -12,37 +12,43 @@ module Fetch(
 	input [31:0] jmppc,
 	output reg bubble = 1,
 	output reg [31:0] insn = 0,
-	output reg [31:0] pc = 0);
-
-	reg [31:0] prevpc;
-	reg [31:0] nextpc;
-	initial
-		prevpc = 32'hFFFFFFFC;	/* ugh... the first pc we request will be this +4 */
-	always @(negedge Nrst)
-		prevpc <= 32'hFFFFFFFC;
-
-	always @(*)	
+	output reg [31:0] pc = 32'hFFFFFFFC);
+	
+	reg qjmp = 0;	/* A jump has been queued up while we were waiting. */
+	reg [31:0] qjmppc;
+	always @(posedge clk or negedge Nrst)
 		if (!Nrst)
-			nextpc = 32'hFFFFFFFC;
-		else if (stall)	/* don't change any internal state */
-			nextpc = prevpc;
-		else if (jmp)
-			nextpc = jmppc;
-		else
-			nextpc = prevpc + 32'h4;
+			qjmp <= 0;
+		else if ((rd_wait || stall) && jmp)
+			{qjmp,qjmppc} <= {jmp, jmppc};
+		else if (!rd_wait && !stall && qjmp)	/* It has already been intoed. */
+			{qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
+	
+	reg [31:0] reqpc;
 	
-	assign rd_addr = nextpc;
-	assign rd_req = !stall;
-			
-	always @(posedge clk)
-	begin
-		if (!rd_wait || !Nrst)
-			prevpc <= nextpc;
-		if (!stall)
-		begin
-			bubble <= rd_wait;
+	/* Output latch logic */
+	assign rd_addr = reqpc;
+	assign rd_req = 1;
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst) begin
+			bubble <= 1;
+			insn <= 0;
+			pc <= 32'h00000000;
+		end else if (!stall) begin
+			bubble <= (jmp || qjmp || rd_wait);
 			insn <= rd_data;
-			pc <= nextpc;
+			pc <= reqpc;
+		end
+	
+	always @(posedge clk or negedge Nrst)
+		if (!Nrst)
+			reqpc <= 0;
+		else if (!stall && !rd_wait) begin
+			if (qjmp)
+				reqpc <= qjmppc;
+			else if (jmp)
+				reqpc <= jmppc;
+			else
+				reqpc <= reqpc + 4;
 		end
-	end
 endmodule